Configurable address line inverter for remapping memory

Details Configurable address line inverter for remapping memory Configurable address line inverter for remapping memory

1997-04-02

1999-11-16

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

395652, G06F 1202

Patent

active

059875810

ABSTRACT:
A flexible memory mapper for selectively inverting the state of an address line on an address bus includes a selectable inverter element and a control circuit. The selectable inverter element has a control input coupled to an output of the control circuit, an input, and an output. The control input, the input, and the output are capable of being in two logic levels. When the control input is in a first logic level, the input is passed through uninverted to the output of the selectable inverter element. When the control input is in a second logic level, the input is passed through inverted to the output of the selectable inverter element. The control circuit output feeds one of two logic levels to the control input of the selectable inverter element, outputting the second logic level in response to an input address within a selected address range and a user selectable input bit, and otherwise outputting the first logic level.

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