Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Reexamination Certificate
2006-03-07
2006-03-07
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
C711S100000, C711S154000, C711S200000, C711S217000
Reexamination Certificate
active
07010664
ABSTRACT:
A configurable address generator includes addressing sequence circuitry such as a set of counters. A set of comparators is also preferably included in the configurable address generator in order to detect different addressing conditions (e.g., full, empty, etc.). Coupled to these components is a plurality of programmable bits that allows the address generator to be configured to meet a number of different design requirements. For example, the configurable address generator can be configured as a stack pointer; it can also be configured to provide address generation for FIFO and MAC-based filter circuits, etc.
REFERENCES:
patent: 4984151 (1991-01-01), Dujari
patent: 5301344 (1994-04-01), Kolchinsky
patent: 5784636 (1998-07-01), Rupp
patent: 6601158 (2003-07-01), Abbott et al.
patent: 6870787 (2005-03-01), Rohleder et al.
Ballagh Jonathan B.
Keller Eric R.
Milne Roger B.
Hernandez Peter
King John
Thai Tuan V.
Xilinx , Inc.
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