Conductor path contacting arrangement and method

Details Conductor path contacting arrangement and method Conductor path contacting arrangement and method

1999-05-26

2001-10-16

Clark, Jhihan B (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

C257S774000, C257S750000, C257S758000, C257S753000, C257S775000

Reexamination Certificate

active

06303990

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a conductor path contacting arrangement for contacting a first conductor path, which is applied on a substrate and covered with a first insulating layer, via a contact hole in the first insulating layer to a second conductor path; as well as to a corresponding conductor path contacting method.
BACKGROUND INFORMATION
Although applicable to the contacting of any conductor paths, the present invention as well as its underlying object are explained with reference to the contacting of a platinum conductor path applied on a silicon substrate and an aluminum bonding land conductor path.
FIGS. 4
a-c
are a schematic depiction of a usual contacting arrangement,
FIG. 4
a
being a plan view,
FIG. 4
b
a cross-sectional view with a positive etching flank for the insulating layer, and
FIG. 4
c
a cross-sectional view with a negative etching flank for the insulating layer.
In
FIGS. 4
a-c
, reference character
10
designates a silicon substrate,
40
a platinum conductor path,
50
a CVD oxide,
53
a positive etching flank,
55
a negative etching flank,
60
an aluminum bonding land conductor path,
61
a web region,
62
a land region,
65
pinched-off aluminum pieces,
67
a detachment edge, L a contact hole, and Rc a contact hole junction resistance.
The arrangement shown in
FIGS. 4
a-c
serves to transition the elongated platinum conductor path
40
, via a narrow web region
61
of aluminum bonding land conductor path
60
, into a wider land region
62
of the aluminum bonding land conductor path
60
.
Platinum conductor path
40
, running on substrate
10
, is first covered completely with the insulating layer made of CVD oxide
50
. In the end region of platinum conductor path
40
, contact hole L is then opened up in CVD oxide
50
using a usual photolithographic etching process. Contact hole L is spaced away from the edges of the end region of platinum conductor path
40
. Deposition and masking of aluminum bonding land conductor path
60
is then performed in order to yield the arrangement shown in
FIG. 4
a.
In order to evaluate the quality of the contact created in this fashion, contact hole junction resistance Rc between contact hole L in CVD oxide
50
and the corresponding land region
62
of aluminum bonding land conductor path
60
is measured.
Measurement of this contact hole junction resistance Rc serves in particular to characterize the degree to which the contact hole flanks are overlaid with aluminum, as will be explained in further detail below with reference to
FIGS. 4
b
and
c.
When contact hole L is opened in wet-chemical fashion, the result is usually the desired positive etching flanks
53
for the CVD oxide, which ensure good overlay of the contact hole flank with aluminum, and thus a low contact hole junction resistance Rc (
FIG. 4
b
).
This standard process can, however, result locally on a wafer in undesired negative etching flanks
55
for the CVD oxide, and thus in high contact hole junction resistances Rc (
FIG. 4
c
). They may be caused by an inhomogeneously grown CVD oxide layer
50
and/or by contaminants at the interface between CVD oxide layer
50
and platinum conductor path
40
. Such negative etching flanks at the contact hole edges result, in particular, in pinched-off pieces
65
and detached edges
67
, which can result in the elevated contact hole junction resistance Rc and, in the worst case, in an break in aluminum bonding land conductor path
60
and thus failure of the component in question. It has proven disadvantageous that with the aforementioned known approach, a certain proportion (typically a few %) of the components exhibit an elevated contact hole junction resistance Rc with the standard process.
SUMMARY OF THE INVENTION
The conductor path contacting arrangement according to the present invention and the corresponding conductor path contacting method have, in contrast to the known approach, the advantage that because of the special contact hole design, the problem of elevated contact hole junction resistance no longer occurs. Reliable contacting, regardless of the contact hole flanks, is achieved, guaranteeing high production quality and yield.
An underlying idea of the present invention is that the contact hole overlies a region above the first conductor and a region, adjacent thereto, of the substrate; and inside the contact hole the second conductor path is stepped down from the contact region having the first conductor path toward the substrate therebeneath. In other words, the second conductor path has a downward step, and not just an upward step onto the insulating layer as in the existing art. In particular, a smaller step height and thus better step overlay is possible for the downward step. This results, by comparison with the standard process, in independence from the thickness of the insulating layer and from the flank slope of the contact hole.
According to a preferred embodiment, the second conductor path lies substantially inside the contact hole and preferably only its edge region lies on the insulating layer.
According to a further preferred embodiment, the second conductor path is a bonding land conductor path having a narrower web region contacted on the first conductor path and a wider land region adjacent thereto.
According to a further preferred embodiment, the first conductor path has an eye-shaped region, such that the edge of the contact hole lies on the eye-shaped region. This is advantageous in particular when a wet-etching method is used, since in this context etching spikes can occur along edges between the first conductor path and the first insulating layer, and can cause the first insulating layer to be at an undefined distance beneath a resist mask which is preferably used.
According to a further preferred embodiment, the edge of the contact hole lies substantially centrally on the eye-shaped region. This helps compensate for process tolerances.
According to a further preferred embodiment, a second insulating layer is provided on the substrate, as an electrical insulator and/or adhesion layer for the first and second conductor paths.
According to a further preferred embodiment, a third insulating layer or conductive layer is provided on the substrate or on the second insulating layer, as an adhesion layer for the first conductor path.
According to a further preferred embodiment, the first and/or second insulating layer comprises multiple insulating layers.
According to a further preferred embodiment, the first and/or second insulating layer includes a combination of electrically conductive a nonconductive layers.


REFERENCES:
patent: 3577036 (1971-05-01), Curtis
patent: 4713682 (1987-12-01), Erie et al.
patent: 4827326 (1989-05-01), Altman et al.
patent: 5106780 (1992-04-01), Higuchi
patent: 5652182 (1997-07-01), Cleeves
patent: 5869393 (1999-02-01), Tseng
patent: 5888911 (1999-03-01), Ngo et al.
patent: 6046104 (2000-04-01), Kepler

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