Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Patent
1998-01-15
2000-06-27
Chaudhuri, Olik
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
257529, 257209, H01L 2900
Patent
active
060810211
ABSTRACT:
An integrated circuit device including a conductor-insulator-conductor structure and a method of manufacturing the structure simultaneously while forming a dual damascene via. A first interconnect layer is formed upon a first interlevel dielectric. Openings extend through a second interlevel dielectric to the first interconnect layer. An insulator is deposited in the openings. A trench is then etched into the upper portion of the openings that will become vias while simultaneously removing the insulator from the bottom of the openings that will become vias. A conductor is then deposited in the openings and in the trenches and chemical-mechanical polishing (CMP) is used to pattern the conductor. A third interlevel dielectric is then deposited, openings are formed extending to the conductors, and third interconnect layer conductors are deposited and patterned.
REFERENCES:
patent: 4481283 (1984-11-01), Kerr et al.
patent: 4959705 (1990-09-01), Lemnios et al.
patent: 5055426 (1991-10-01), Manning
patent: 5233217 (1993-08-01), Dixit et al.
patent: 5262354 (1993-11-01), Cote et al.
patent: 5322812 (1994-06-01), Dixit et al.
patent: 5396094 (1995-03-01), Matsuo
patent: 5406447 (1995-04-01), Miyazaki
patent: 5447880 (1995-09-01), Lee et al.
patent: 5451551 (1995-09-01), Krishnan et al.
patent: 5459100 (1995-10-01), Choi
patent: 5479316 (1995-12-01), Smrtic et al.
patent: 5502000 (1996-03-01), Look et al.
patent: 5521423 (1996-05-01), Shinriki et al.
patent: 5550400 (1996-08-01), Takagi et al.
patent: 5576240 (1996-11-01), Radosevich et al.
patent: 5602053 (1997-02-01), Zheng et al.
patent: 5619063 (1997-04-01), Chen et al.
patent: 5641985 (1997-06-01), Tamura et al.
patent: 5798297 (1998-08-01), Winnerl et al.
Vertical Capacitor VLSI Structure for High Voltage Applications; IBM Technical Disclosure Bulletin, vol. 32 (7), 37-41 (1989).
J.H. Ha et al., Reduction of Loading Effect by Tungsten Etchback in a Magnetically Enhanced Reactive Ion Etcher, IEEE Transactions on Semiconductor Mfg., vol. 9 (2), 289-91 (1996).
C. Hu, Interconnect Devices for Field Programmable Gate Array, IEDM, 591-94 (1992).
S. Chiang et al, Antifuse Structure for Field Programmable Gate Arrays, IEDM, 611-14 (1992).
K.E. Gordon et al., Conducting Filament of the Programmed Metal Electrode Amorphous Silicon Antifuse, IEDM, 27-30 (1993).
Appln. No. 08/752,137, filed Nov. 19, 1996, entitled "Advanced Damascene Planar Stack Capacitor Fabrication Method", IBM Docket # HQ9-96-013.
Gambino Jeffrey P.
Kirihata Toshiaki
Narayan Chandrasekhar
Cao Phat X.
Chaudhuri Olik
International Business Machines - Corporation
LandOfFree
Conductor-insulator-conductor structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Conductor-insulator-conductor structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Conductor-insulator-conductor structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1786647