Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2006-09-05
2006-09-05
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S701000
Reexamination Certificate
active
07102222
ABSTRACT:
A conductive trace structure and a semiconductor package having the conductive trace structure are provided. A plurality of conductive traces are formed in and surrounding a chip mounting area on a substrate, for mounting a chip on the chip mounting area. Widened portions are formed on the conductive traces in the chip mounting area and at positions across a periphery of the chip mounting area, the widened portions having a line width larger than that of the rest part of the conductive traces. The widened portions of the conductive traces can sustain concentrated thermal stress from the peripheral area of the chip caused by mismatch in coefficient of thermal expansion between the chip and the substrate. This prevents the conductive traces that pass through the periphery of the chip mounting area from cracks or breaks due to the thermal stress, thereby improving the reliability and yield of the semiconductor package.
REFERENCES:
patent: 5399903 (1995-03-01), Rostoker et al.
patent: 5903051 (1999-05-01), Miks et al.
patent: 6268568 (2001-07-01), Kim
Chiang Chin-Chien
Kuo Kuan-Ting
Lai Yu-Ting
Corless Peter F.
Edwards Angell Palmer & & Dodge LLP
Jensen Steven M.
Potter Roy
Siliconware Precision Industries Co. Ltd.
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