Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-08
2004-03-30
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S369000, C257S758000
Reexamination Certificate
active
06713823
ABSTRACT:
BACKGROUND
The present invention relates generally to conductive routings in integrated circuits, and more particularly to conductive routings in integrated circuits that provide substantially continuous conductive planes for the flow of electrical currents.
Integrated circuits (“IC”), which generally refer to electronic circuits formed on a silicon or other semiconductor substrate, have widespread application in modem electronic systems. An IC chip may contain circuit devices, such as transistors, and electrical interconnects, such as lead lines to electrically couple the circuit devices. An IC chip may also contain conductive pads for providing electrical couplings of the chip to external devices, such as voltage sources and control circuits.
Traditionally, multiple conductive or metal layers in a chip provide conductive couplings between the terminals of transistors and conducting pads. Therefore, an IC chip having one or more transistors may have metal or conductive interconnects that electrically couple the source and drain regions of the transistors to the conducting pads of the IC chip. In the typical implementations of conducting pads for bond-wire-packaged chips, the conducting pads are arranged along the perimeter of the chips, and not above the functional area of transistors or other devices. More specifically, for an IC chip with vertical field effect transistors (“FETs”), source pads are arranged along the periphery of the top surface of a semiconductor substrate, and a drain connection is provided by a bulk semiconductor connection on backside. Therefore, in order to electrically couple doped regions in a substrate to conducting pads, metal lines are arranged to provide axial current flow through several metal layers and vias.
However, several concerns arise if the metal lines have an excessive length. First, increasing the length of the metal lines creates additional resistance for and power loss by the circuit. For modern applications of IC chips in portable devices, power loss as a result of increased resistance consumes additional electrical power and reduces the battery life of the portable devices. Second, the increased resistance and power loss also lead to heat dissipation problems that restrain the design and layout arrangement of the IC chip. The increased current density in conductive interconnects reduces the long-term reliability of a circuit. Third, providing additional area for conducting pads reduces the area available for functional devices, such as transistors, capacitors, resistors, and inductors. This inefficient layout increases the size and manufacturing cost of IC chips and associated packages.
In view of the foregoing, it would be advantageous to develop an IC structure with lower resistance, reduced power loss, and increased area for functional devices.
SUMMARY
In one aspect, the invention is directed to an integrated circuit structure with a first layer and a second layer. The first layer has a first conductive area and a second conductive area electrically isolated from the first conductive area. The first conductive area has an extended region at an edge of the first conductive area, and the extended region of the first conductive area protrudes into the second conductive area. The second layer is positioned over the first layer and has a third conductive area and a fourth conductive area electrically isolated from the third conductive area. The fourth conductive area has an extended region at an edge of the fourth conductive area that is electrically coupled to the extended region of the first conductive area.
In another aspect, the invention is directed to an integrated circuit structure with a substrate and a first layer over the substrate. The substrate has a first plurality of doped regions and a second plurality of doped regions. The first layer has a first conductive area that is a substantially continuous plane of a conductive material to provide a conductive coupling to the first plurality of doped regions covered by the first conductive area. The first conductive area has at least one isolated structure within the first conductive area to provide a conductive coupling between a second layer above the first conductive area and the second plurality of doped regions covered by the first conductive area.
Advantages of the invention may include the following. The lengths of conductive routings from doped regions in a substrate to conducting pads can be shortened. Interconnection resistance and power loss can be reduced. In addition, the conductive routing structure of the present invention can permit planar current flow so as to reduce resistance and current flow density, thereby increasing the reliability of circuits and devices. The area needed for providing conducting pads on an IC chip can be reduced. As a result, a chip implemented with the present invention can have cheaper dies in a smaller package, lower power loss, and shorter conductive path lengths than a traditional IC structure. The area available for functional devices in a chip, therefore, can be increased. At the same time, the performance of devices and circuits on a chip can be increased as a result of reduced resistance and power loss.
REFERENCES:
patent: 4636825 (1987-01-01), Baynes
patent: 4821084 (1989-04-01), Kinugasa
patent: 6084266 (2000-07-01), Jan
patent: 6278264 (2001-08-01), Burstein et al.
Fish & Richardson P.C.
Munson Gene M.
Volterra Semiconductor Corporation
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