Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-02-21
2001-08-21
Picard, Leo P. (Department: 2835)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S757000, C257S765000
Reexamination Certificate
active
06278150
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a conductive layer connecting structure and a method of manufacturing the same, and in particular to a conductive layer connecting structure used in a semiconductor device as well as a method of manufacturing the same.
2. Description of the Background Art
Demands for semiconductor memory devices have been rapidly increased owing to rapid and wide spread of information equipments such as computers. Regarding a function, devices having a large-scale storage capacity and a high operation speed have been demanded. In view of this, technical development has been made for improving a density, a responsibility and a reliability of semiconductor memory devices.
DRAMs (Dynamic Random Access Memories) are well known as a kind of semiconductor memory devices allowing random input/output of storage information. For improving a density of the DRAM, a memory cell size must be reduced. As the memory cell size is reduced, a planar area occupied by a capacitor is also reduced. This results in reduction in quantity of charges which can be stored in the capacity (i.e., quantity of charges which can be stored in the memory cell of 1 bit). If the quantity of charges storable in the memory cell of 1 bit is lower than a predetermined value, the DRAM functioning as a storage region performs an instable operation, and the reliability lowers.
In order to prevent an instable operation of the DRAM, it is necessary to increase a capacity of the capacitor while keeping an occupied planar area within a predetermined range. As measures for increasing a capacity of the capacitor, measures such as (1) reduction in thickness of a capacitor dielectric film, and (2) increase in a dielectric constant of the capacitor dielectric film have been studied.
Reduction in thickness of the capacitor dielectric film at the above item (1) has already been achieved to a maximum extent in a usual structure using a silicon oxide film as the capacitor dielectric film. Therefore, the capacitor must have a complicated form such as a cylindrical form or a fin-like form so as to increase the capacitor capacity using the silicon oxide film as the capacitor dielectric film. However, an extremely complicated process is required for manufacturing the capacitor having the above complicated form.
Accordingly, development for increasing the capacitor dielectric constant in the above item (2) has recently been made. In order to increase the dielectric constant of the capacitor dielectric film, the capacitor dielectric film may be made of a material having a high dielectric constant which is called a high dielectric constant material. This high dielectric constant material generally has a dielectric constant which is several to hundreds of times larger than that of a silicon oxide film. By using the high dielectric constant material as the capacitor dielectric film, the capacity can be increased without complicating a form of the capacitor.
Materials called high dielectric constant materials are, for example, tantalum pentoxide (Ta
2
O
5
), lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), strontium titanate (STO) and barium titanate (BTO) and barium strontium titanate (BST).
Since these high dielectric constant materials are crystallizable, platinum group elements having lattice constants close to that of high dielectric constant material is used at a portion which is in contact with the high dielectric constant material. Therefore, the capacitor of the conventional DRAM has a conductive layer connecting structure in which platinum group elements are electrically connected to a silicon substrate.
However, the platinum group elements have high reactivity with elements such as silicon. In a structure where the platinum group elements and the silicon are in contact with each other, thermal processing at a temperature of 400° C. easily causes a solid phase reaction, by which, for example, platinum silicide is formed between platinum and silicon. This changes a crystal structure of platinum, and prevents epitaxial growth of the high dielectric constant material at the surface of platinum. When the high dielectric constant material is to be formed, an oxidizing atmosphere is required, in which platinum silicide is oxidized to form a silicon oxide film at the surface of platinum silicide. This silicon oxide film has a lower dielectric constant than the high dielectric constant material, so that it reduces the dielectric constant of the dielectric film.
In order to use a high dielectric constant material as a dielectric film of a capacitor, therefore, a layer for preventing diffusion is required between a lower electrode layer made of platinum and a conductive layer made of polycrystalline silicon as well as between an upper electrode layer made of platinum and an interconnection layer on the capacitor. Generally, diffusion preventing layers are formed of titanium nitride which is widely used as barrier metal for aluminum interconnection layers. It is known that such diffusion preventing layers can property function at up to about 500° C.
The following references have disclose DRAMs having capacitors which use the high dielectric constant material as capacitor dielectric films.
(1) Japanese Patent Laying-Open No. 7-38068 (1995).
(2) International Electron Devices Meeting (IEDM) 92, pp. 267-270.
A DRAM disclosed in the above reference (1) will be described below with reference to the drawings.
FIG. 33
is a cross section showing a conductive layer connecting structure in a DRAM disclosed in Japanese Patent Laying-Open No. 7-38068. Referring to
FIG. 33
, isolation oxide film
1033
s
are formed at a surface of a silicon substrate
1031
. Channel stopper regions
1035
are in contact with the lower surfaces of isolation oxide films
1033
, respectively. A plurality of transfer gate transistors
1030
are formed at the surface of silicon substrate
1031
electrically isolated by isolation oxide films
1033
and channel stopper regions
1035
.
Each transfer gate transistor
1030
has a gate oxide film
1021
, a gate electrode
1023
and impurity regions
1025
. Gate electrode
1023
is formed on a region between impurity regions
1025
with gate oxide film
1021
therebetween. A silicon oxide film
1027
covers the surface of gate electrode
1023
.
There is formed a bit line
1037
, which extends over the surface of silicon oxide film
1027
and is in contact with one of impurity regions
1025
. Bit line
1037
and transfer gate transistor
1030
are covered with silicon oxide film
1001
and silicon nitride film
1003
.
Silicon nitride film
1003
is layered over silicon oxide film
1001
. Since bit line
1037
is covered with silicon oxide film
1001
and silicon nitride film
1003
, it forms a buried bit line.
Silicon oxide film
1001
and silicon nitride film
1003
are provided with contact holes
1001
a
and
1003
a
reaching the surfaces of impurity regions
1025
. Contact holes
1001
a
and
1003
a
are filled with plug layers
1009
a
which are in contact with impurity regions
1025
.
Capacitors
1020
are electrically connected to impurity regions
1025
via plug layers
1009
a
, respectively.
Each capacitor
1020
has a lower electrode layer
1013
a
, a capacitor dielectric film
1015
and an upper electrode layer
1017
. The lower electrode layer
1013
a
is formed over the surface of silicon nitride film
1003
with a barrier layer
1011
a
therebetween, and has a film thickness from
30
to 100 nm. Lower electrode layer
1013
a
is made of platinum (Pt).
Barrier layer
1011
a
has a three-layer structure made of titanium (Ti), titanium nitride (TiN) and titanium (Ti), and is in contact with plug layer
1009
a
. Each of films forming barrier layer
1011
a
has a thickness from 10 to 50 nm. Barrier layer
1011
a
prevents diffusion of impurity from plug layer
1009
a
made of doped polycrystalline silicon into lower electrode
1013
a
, and also serves to improve adhesion between silicon nitride film
1003
and lower electrode layer
Kashihara Keiichiro
Okudaira Tomonori
Tsunemine Yoshikazu
Duong Hung Van
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Picard Leo P.
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