Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Reexamination Certificate
2003-06-10
2004-06-08
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
C257S690000
Reexamination Certificate
active
06747360
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device sealed with molding resin, i.e., a plastic package. More particularly, the present invention relates to a plastic package in which a copper plate or similar metal plate provides electric connection between the electrodes of a semiconductor chip and lead terminals.
2. Description of the Background Art
It is a common practice with a plastic package to mount a semiconductor chip to the island portion of a lead frame, connect the inner leads of the lead frame and electrodes formed on the front of the chip with gold wires or similar bonding wires, and then seal the entire assembly with molding resin. When the chip is mounted to the island portion, use is made of a die bonding material implemented by conductive resin consisting of epoxy resin and silver filled therein. The die bonding material is introduced between the chip and the island portion and then hardened by baking. The bonding wires are connected by the combination of thermo-compression bonding and ultrasonic wave. When a power transistor or similar power device for great current applications should be sealed by the method described above, the bonding wires formed of gold are increased in diameter for lowering wiring resistance.
The conventional semiconductor device described above has sufficient reliability as determined by TCTs (Temperature Cycling Tests) and PCTs (Pressure Cooker Tests). However, the problem is that gold increases the cost of the semiconductor device with an increase in the size of the power device, limiting the diameter of the bonding wires. In light of this, Japanese Patent Laid-Open Publication No. 2000-114445 proposes a method that connects the electrodes of a semiconductor chip and the source terminal of a lead frame with a metal plate instead of a bonding wire.
We conducted a series of researches and experiments with the method taught in the document mentioned above and found that the method had some problems left unsolved, as will be described specifically later.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide conductive hardening resin for a semiconductor device that frees the electrodes of a semiconductor chip, a wiring member (lead frame) and a metal plate from peeling even in the event of TCTs and PCTs and prevents conductivity from being lowered.
Conductive hardening resin for a semiconductor device of the present invention contains metal powder for providing electric conduction between electrodes positioned on the front of a semiconductor chip and a wiring material including lead terminals via a conductive plate. The resin has a modulus of elasticity of 2.0×10
9
Pa or below when hardened.
A semiconductor device using the above resin is also disclosed.
REFERENCES:
patent: 5667884 (1997-09-01), Bolger
patent: 6459147 (2002-10-01), Crowley et al.
patent: 2003/0102573 (2003-06-01), Tanabe et al.
patent: 2000-114445 (2001-04-01), None
Fukuizumi Akira
Oonami Kazuto
Cao Phat X.
NEC Electronics Corporation
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