Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
1997-08-22
2001-08-07
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S778000, C257S783000
Reexamination Certificate
active
06271598
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the production of memory modules and other multi-chip electronic assemblies, and more particularly to a flip chip apparatus for interconnecting multiple die or chips.
There is an ongoing demand for additional semiconductor memory in personal computing applications. One practice is for systems manufacturers to ship personal computer systems with a minimum amount of memory installed and provide a way for the owners to add additional memory as their needs dictate. This protects the manufacturer from sometimes being on the wrong side of a price swing in the volatile semiconductor memory market and also lowers the price of the system being sold.
This practice creates a huge market for low cost, reliable memory modules that can be installed after the initial sale, either by users or other individuals that are not necessarily skilled in the art of computer hardware modification.
The physical need for this market has been met with memory modules such as the 88 pin Personal Computer Memory Card International Association (PCMCIA) card and a variety of Single In-line Memory Modules (known as SIMMs). These devices typically include a printed circuit board (PCB) and a number of discrete integrated circuit memory chips connected to the PCB in a manner that allows the PCB to be easily installed in a computer system.
One problem with the current technology is cost, since users are looking for the lowest cost solution to their memory storage needs. Current technology generally provides two methods of manufacturing memory modules. The most common method is to first package individual semiconductor chips into individual plastic packages, test each chip, and then attach the packages to a PCB, using a multi-step process. The multi-step process includes the steps of attaching the chips to a lead frame, connecting wires to the frame, injection molding the frame, plating the leads with tin, deflashing the molding compounds, bending the leads, testing the package, and so on. Such a multi-step process is both cumbersome and expensive.
Another method for manufacturing memory modules is commonly referred to as “flip chip” technology, which utilizes solder balls to solder chips face-down on a substrate. Flip chips are typically used to create multichip memory modules. One disadvantage of conventional flip chips is that the thermal expansion/contraction properties of the materials used in the manufacturing process must be matched closely to prevent damage to the flip chips during use. Another disadvantage is that standard visual inspections cannot be performed on the flip chips, because the flip chips are attached face-down on the substrate, covering the connection with the substrate.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an improved flip chip apparatus.
In one preferred embodiment, the present invention provides a flip chip assembly including a first flip chip; a second flip chip directly connected to the top of the first flip chip; and electrically conductive epoxy means disposed between the second flip chip and the top of the first flip chip to form an electrical connection between the first flip chip and the second flip chip.
In another preferred embodiment, the present invention provides a flip chip assembly including a plurality of semiconductor chips where the plurality of chips are vertically interconnected on top of one another to form an electrically interconnected stack of chips; a flip chip directly connected to the top chip of the stack of chips; and electrically conductive epoxy means disposed between said flip chip and said top chip to form an electrical connection between the flip chip and the top chip.
In still another preferred embodiment, the present invention provides a flip chip assembly including a semiconductor wafer having a plurality of first flip-chips formed thereon; a plurality of second flip chips, each one of the second flip chips directly connected to a respective one of the plurality of first flip-chips; and electrically conductive epoxy means disposed between the respective first flip-chip and second flip-chip connections to form an electrical connection between the respective first flip-chip and second flip chip connections.
In still another preferred embodiment, the present invention provides an apparatus for producing a multichip assembly including a first flip chip and a second flip-chip. Each of the first and second flip chips include inner bond pads that are rerouted to other areas on the respective flip-chip to facilitate connection with the other flip-chip. The inner bonds are rerouted by covering each chip with a first insulation layer and opening the first insulation layer over the inner bond pads. A metal layer is then disposed over the first insulation layer in contact with the inner bond pads. A second insulation layer is disposed over the metal layer, and the second insulation layer is opened to expose selected portions of the metal layer to form external connection points. Electrically conductive epoxy is then disposed between the external connection points of each of the first and second flip chips, thereby electrically interconnecting the first and second flip-chips.
Other objects, features and advantages of the present invention will become apparent from the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 3648131 (1972-03-01), Stuby
patent: 4074342 (1978-02-01), Honn et al.
patent: 5625230 (1997-04-01), Park et al.
patent: 5675180 (1997-10-01), Pederson et al.
patent: 0314437 (1989-05-01), None
Robinson Marc E.
Scharrenberg William R.
Vindasius Alfons
Clark Sheila V.
Cubic Memory Inc.
Trial & Technology Law Group
LandOfFree
Conductive epoxy flip-chip on chip does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Conductive epoxy flip-chip on chip, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Conductive epoxy flip-chip on chip will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2444352