Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-01-17
2002-10-01
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S106000, C438S108000, C438S109000, C257S776000, C257S777000, C257S778000
Reexamination Certificate
active
06458623
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electronic assemblies, and in particular, to electrically and mechanically connecting two electronic components to form an electronic assembly having reduced thermo-mechanical fatigue, while also providing the electronic assembly with the ability to use existing bond and assembly technologies in addition to providing the assembly with reworkability.
2. Description of Related Art
Forming electronic assemblies by electrically connecting two components such as a multi-layer ceramic package or circuit chip to a card, board, or another connector is well known in the art. Such multi-layer electronic assembly formation is referred to in the art as surface mount technology which can include, but is not limited to, solder join, flip chip, C4, ball grid array and pin grid array. As will be recognized, surface mount technology has gained acceptance as the preferred means of joining electronic package assemblies, particularly in high end computers.
Over the years, surface mount technology has been accomplished by a variety of techniques such as, for example, the use of interposers, soldering techniques, conductive adhesives, and the like. Prior art is directed to using thermoplastic interposers, typically a fully cross-linked high modulus material with very low compliance, having a plurality of cure stages for use in surface mount technology whereby the interposer can be positioned between any two mating surfaces having connector arrays. The interposer may be provided with holes which can be filled with solder or a conductive adhesive to connect the two substrates to the interposer. Typically, the interposer is then permanently bonded to both components through heat and pressure. However, as a result of the interposer comprising a thermoplastic polymer, the interposer is typically made of a high modulus non-compliant material which does not alleviate CTE mismatch induced strain through material movement. The adhesion of the interposer to both electronic components of the assembly typically induces a strain gradient across the interposer. In an assembly having a strong bond between the interposer and the electronic components, the interposer may influence the CTE related movement of each component and thus minimize both the difference in material movement and the strain, potentially resulting in an electronic assembly having increased working life. However, such technology relies on strong, typically permanent, bonds between the interposer and both electronic components, and thereby is not compatible with electronic assemblies requiring or desiring the ability of component reworkability.
In addition to the introduction of interposers for use in surface mount technology, numerous solder structures have been proposed for surface mounting. Typical surface mount processes form solder structures by screening solder paste onto conductive pads exposed on the surface of the first electronic substrate. The solder paste is reflowed typically in a hydrogen atmosphere and homogenizes the pad and brings the solder into a spherical shape which is then aligned to corresponding pads on the electronic structure or board to be connected thereto. After alignment, the substrate and board go through a reflow operation to melt the solder and create a solder bond between the corresponding pads on the substrate and other electronic component. However, such soldering techniques produce solder bonds of very small height leading to decreased strain absorption capability, as well as costly high temperature reflows as a result of the double reflow operations.
Semiconductor chips and multilayer ceramic or organic electronic components are also joined together by Controlled Collapse Chip Connection on a surface of one of the electronic components to corresponding pads on the surface of the other component. Controlled Collapse Chip Connection (C4) is an interconnect technology developed by IBM as an alternative to wire bonding. C4 technology provides a more exact and somewhat greater quantity of solder to be applied than can be applied through screening. In the C4 interconnect technology, a relatively small solder bump or solder ball is attached to pads on one of the components being joined, therein the conventional chip joining technology providing for semiconductor chip and ceramic or organic substrates to be attached to each other. The electrical and mechanical interconnects are then formed by positioning the corresponding pads on the other electronic component adjacent the solder bumps and reflowing the bumps at an elevated temperature. The C4 joining process is self-aligning in that the wetting action of the solder will align the chip bump pattern to the corresponding substrate pads.
Further techniques for mechanically and electrically connecting various components in surface mount technology include providing a module with a ball grid array (BGA) of solder balls In such techniques, balls of solder are arranged in a predetermined pattern on the module corresponding to a pattern of attachment pads on a substrate, typically referred to as a footprint. The solder balls of the module may then be aligned to the attachment pads of the substrate. Typically, a solder paste may be applied to the attachment pads on the substrate to provide the flux required and also cause the solder balls to adhere to the attachment pads to maintaining alignment with the solder balls during heating and reflow of the solder to form the assembly.
C4 technology (chip to substrate connection) and BGA technology (substrate to board) offer advantages of low cost, high I/O density, low inductance surface mounting interconnection, potentially smaller packages, as well as robust processing steps. However, these area array technologies are limited by strain absorption due to the allowable diameter of the solder sphere. Typically, C4 bumps are 3-5 mils in diameter while BGA solder balls are approximately 20-35 mils in diameter, whereby the size of the bump or solder ball determines the fine pitch capability, as well as the strain absorption of the interconnect with a coefficient of thermal expansion (CTE) mismatch between the chip and substrate, or substrate and board. For example, the CTE mismatch may be about 15 ppm/°C. for a glass-ceramic module on an FR-4 (fiber-reinforced epoxy) card.
During normal operations, the entire module is subject to temperature excursions due to the functioning of the circuits on the chip, resistance heating of the solder joints, the wiring within the chip, and the wiring within the substrate. This heating results in the expansion and contraction of all of these components as temperatures rise and fall. Chips are primarily comprised of silicon, which has a coefficient of thermal expansion in the range of about 3.0 ppm/°C. The corresponding substrates to which the chips are joined are typically made of ceramic or organic materials, which have coefficients of thermal expansion in the ranges of about 3 to about 7 ppm/°C. and about 12 to about 20 ppm/°C., respectively, while the corresponding printed circuit board typically has a coefficient of thermal expansion in the ranges of about 15 to about 22 ppm/°C. As a result, the chip and the substrate, and substrate and card expand and contract at different rates during thermal cycling. This mismatch places stresses on the solder joints, and over time results in the fatigue of the solder joints. Eventually, continual stress causes cracks to propagate completely across the solder joints leading to electrical failure of the electronic module.
Multilayer ceramic electronic components are also joined to printed circuit boards using high melt columns in place of the spheres which are joined to the corresponding metal pads on the surface of each component with a lower melting solder. Column grid array (CGA) technology permits greater strain absorption than conventional BGA due to the increased joint height, while simultaneously allowing the capability of finer pitch. Thus, the greater strain absorptio
Goldmann Lewis S.
Interrante Mario J.
Jackson Raymond A.
Ostrander Amy B.
Perry Charles H.
Cioffi James J.
Delio & Peterson LLC
Keshavan B V.
Smith Matthew
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