Conducting layer in chip package module

Details Conducting layer in chip package module Conducting layer in chip package module

2007-01-25

2009-08-18

Le, Thao X (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Insulating material

C438S116000

Reexamination Certificate

active

07576425

ABSTRACT:
A conducting layer in a chip package module includes one or a plurality of through hole penetrating the top of a base being disposed at the bottom of an insulating layer in the chip package module, and inner wall of the through hole being applied with insulation material so that the conductive layer subsequently constructed to the peripheral of the insulation layer may pass the through hole to extend to where above the base before construction of a masking layer and multiple circuit pins to complete construction of the conducting layer that is totally enveloped so to prevent easy oxidization at the conducting layer and improve stability of the chip package to avoid breaking up due to external force applied.

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patent: 6531328 (2003-03-01), Chen
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patent: 6894358 (2005-05-01), Leib et al.
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patent: 7160478 (2007-01-01), Leib et al.
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patent: 7285834 (2007-10-01), Leib et al.
patent: 2004/0222433 (2004-11-01), Mazzochette et al.
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patent: 2001-351997 (2001-12-01), None
patent: 2005/004195 (2005-01-01), None

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