Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2001-01-18
2002-04-09
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C326S044000, C326S049000
Reexamination Certificate
active
06369608
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to conditioning transistors, and more particularly to conditioning semiconductor-on-insulator transistors in programmable logic devices.
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) are a well-known type of a programmable integrated circuit. These devices may be programmed by a user to perform specified functions. Examples of PLDs are field-programmable gate arrays (FPGAs), programmable logic arrays (PLAs) and programmable array logic devices (PALs).
An FPGA comprises an array of configurable logic blocks (CLBs), input/output blocks (IOBs), and a programmable interconnect network. The FPGA conventionally comprises configuration memory cells for configuring the CLBS, IOBS, and interconnect. CLBs are connectable to one another and to IOBs through the programmable interconnect network. By connectable it is meant to include coupled through one or more circuit elements employed for coupling circuit elements to one another, including without limitation circuit elements used for buffering signals. More information on PLD architectures may be found in U.S. Pat. No. Re. 34,444, reissued Nov. 16, 1993 to Kaplinsky (deceased), U.S. Pat. No. Re. 34,363, reissued Aug. 31, 1993 to Freeman (deceased), U.S. Pat. No. 4,642,487, issued Feb. 10, 1987 to Carter, and U.S. Pat. No. 5,914,616 issued Jun. 22, 1999 to Young et al.
CLBs are configured to provide one or more logic functions, including, but not limited to, an AND gate, a NAND gate, an OR gate, an exclusive OR gate, a NOR gate, an exclusive NOR gate, an inverter, a latch, a flip-flop, and combinations thereof to provide functional elements. In particular, CLBs are configured by control signals supplied to control logic. More information on CLB configurable functions may be found in U.S. Pat. No. 5,349,250, issued Sep. 20, 1994 to New.
The programmable interconnect network comprises programmable interconnection points (PIPs) for configuring connections between a plurality of conductive interconnect lines. These conductive interconnect linesmay be of varying lengths. Shorter length lines are called “single length lines” or “singles,” (a single length line spans a single CLB) or “doubles” (spans two CLBs). Somewhat longer intermediate-length lines include “hex lines” or “hexes,” (spans six CLBs) and longer lengths lines “long lines” span
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CLBs, half a column, or a whole column (or row). More information on such an interconnect line length hierarchy may be found in U.S. Pat. No. 5,914,616, issued Jun. 22, 1999 to Young et al.
Owing to resistive-capacitive (RC) time delays of doubles, hexes and long lines, these types of lines are conventionally buffered. Buffering amplifies a passing signal. More information on buffered routing may be found in U.S. Pat. No. 4,855,619 issued Aug. 8, 1989 to Hsieh et al. and U.S. Pat. No. 4,835,418 issued May 30, 1989 to Hsieh.
Accordingly, the FPGA may be used to implement a circuit design. To configure an FPGA to implement a circuit design, configuration data is loaded into the configuration memory cells internal to the FPGA. This configuration data selects functions performed by the CLBs, determines whether the IOBs are used for input, output, or both and establishes slew rate and other characteristics for interfacing with external devices. Configuration data may also provide information regarding circuit operation, such as timing requirements, initial conditions, and other circuit operation information. Conventionally, configuration data is supplied as a bitstream converted from a circuit definition language, such as Verilog, VHDL, or other circuit simulation language. More information on high-level circuit design may be found in U.S. Pat. No. 5,499,192, issued Mar. 12, 1996 to Knapp et al.
FPGAs may be manufactured using a semiconductor-on-insulator, or more particularly a silicon-on-insulator (SOI), structure. Conventionally, an SOI structure comprises two slices of single crystalline silicon separated by silicon oxide.
SOI transistors have what has been termed a “floating body,” namely, an electrically floating semiconductor portion. Charge, having little opportunity to dissipate, can accumulate on the “floating body.” This accumulated charge affects switching speed of SOI transistors. For example, initial or unbiased operation of an SOI transistor may be slower than subsequent or biased operation of the same SOI transistor owing to charge build-up. Thus, SOI transistor delay is operationally variable. To exacerbate the variability of SOI transistor delay, charge may leak-off the floating body between switching events. This variability makes accurate modeling to account for SOI transistor delay in circuit designs problematic.
Conventionally, FPGAs come with “speed files.” “Speed files” contain information used to predict delays in an FPGA. These delays are in turn used to predict signal propagation times for a circuit design implemented in the FPGA. Worst-case delay values may be used to ensure the implemented circuit design will work in accordance with specified parameters. More information on determining timing characteristics may be found in U.S. Pat. No. 5,790,479 issued Aug. 4, 1998 to Conn and U.S. Pat. No. 6,075,418 issued Jun. 13, 2000 to Kingsley et al. However, operation of an SOI transistor may be considerably faster than an equivalent non-SOI transistor, so guaranteeing worst-case values may lead to substantially less than optimal designs.
Therefore, a need exists in the art for a PLD with operationally less variability of SOI transistor switching speed.
SUMMARY OF THE INVENTION
An aspect of the present invention is a method for preconditioning at least one transistor in a programmable logic device formed on a semiconductor-on-insulator structure. More particularly, configuration data is loaded into the programmable logic device. The programmable logic device is configured in response to the configuration data, and the at least one transistor to be preconditioned is identified by the configuring of the programmable logic device. To precondition the at least one transistor, the at least one transistor is switched between on and off states for accumulating charge.
Advantageously, by preconditioning a programmable logic device, switching speeds of transistors are increased, particularly for initial operation thereof. Accordingly, design rules using these faster switching speeds may be used. Moreover, not all transistors in a programmable logic device need to be preconditioned, saving both power and time. That is, preconditioning is limited to those transistors associated with logic nodes in use, as identified by configuration data.
The above, as well as additional aspects of the present invention, will become apparent in the following detailed written description.
BRIEF DESCRIPTION OF THE DRAWINGS
The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:
FIG. 1
is a schematic diagram depicting an exemplary portion of an embodiment of a configured FPGA in accordance with an aspect of the present invention;
FIG. 1A
depicts a cross-sectional view of two transistors formed in a semiconductor-on-insulator structure.
FIG. 2
is a schematic diagram depicting an exemplary embodiment of a prior art FPGA mode select circuit for buffered stages;
FIG. 3
is a schematic diagram depicting an exemplary embodiment of a FPGA mode select circuit for buffered stages in accordance with an aspect of the present invention;
FIG. 4
is a schematic diagram depicting an exemplary embodiment of a prior art FPGA mode select circuit for unbuffered stages;
FIG. 5
is a schematic diagram depicting an exemplary embodiment of a FPGA mode select circuit for unbuffered stages in accordance with an aspect of the present invention;
FIG. 6A
is a block diagram depicting an exemplary portion of a pre-configuration process in accordance with an aspect of the present invention;
FIG. 6B
is a schematic diagram depicting an exemplary embodiment of
Francis Robert J.
Lesea Austin H.
Le Don Phu
Tokar Michael
Webostad W. Eric
Xillinx, Inc.
Young Edel M.
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