Conditional sum adder using pass-transistor logic and integrated

Details Conditional sum adder using pass-transistor logic and integrated Conditional sum adder using pass-transistor logic and integrated

1997-12-18

2000-01-04

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708710, 708629, G06F 750, G06F 752

Patent

active

060120797

ABSTRACT:
Disclosed is an integrated pass-transistor logic circuit which includes a conditional sum adder. This sum adder has seven sum generation blocks of module form and two carry generation blocks. With the sum adder, before carry propagation which is generated through multiplexer chain in respective sum generation blocks arrives at the final stage of the multiplexer chain, the final stage is driven by block carry signals BC.sub.i and /BC.sub.i provided from the respective carry generation blocks. The carry generation and the sum generation occur individually in the conditional sum adder. The sum generation blocks are constituted with pass-transistor logic and the carry generation blocks with Complementary Metal Oxide Semiconductor (CMOS) logic, the sum adder has a more faster operation speed and a more lower power dissipation, as compared with the prior art conditional sum adder having either the pass-transistor logic or the CMOS logic.

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Norio Ohkubo, Makoto Suzuki, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, and Yoshinobu Nakagome "A 4.4 ns CMOS 54.times.54-b Multiplier Using Pass-Transistor Multiplexer", Mar. 1995, IEEE Journal of Solid-State Circuits, vol. 30, No. 3, pp. 251-256.

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