Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1996-12-23
2000-02-15
Santamauro, Jon
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326 98, H03K 1900
Patent
active
060257415
ABSTRACT:
A circuit for conditionally restoring an execution unit in a computer processor, to reduce power consumption. Execution units, such as an arithmetic logic unit, shift/rotate unit, multiply unit, etc., have bits in transit that flow through a series of logic gates. These gates must be precharged after an operation has occurred to prepare the unit for the next operation. The conditional restore circuit evaluates either the data input to the execution unit, or the data output from the execution unit, to determine whether an operation has occurred. The precharge device for the execution is turned on only when the evaluation indicates that an operation has just occurred. The circuit includes an AND gate whose output controls the precharge device, and whose inputs include one line from the evaluation circuit, and one line for cycling (the system clock). In an embodiment wherein the execution unit has two operand multiplexers which receive the data input, the evaluation circuit includes two select line respectively connected to the multiplexers, and to inputs of the AND gate. In an alternative embodiment wherein the execution unit has data output in the form of a TRUE line and a COMPLEMENTARY line, the evaluation circuit includes a NOR gate means having a first input connected to said TRUE line, a second input connected to said COMPLEMENTARY line, and an output connected to said first input of the AND gate.
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Ciraula Michael Kevin
Lattimore George McNeil
Yeung Gus Wai-Yan
Dillon Andrew J.
England Anthony V. S.
International Business Machines - Corporation
Musgrove Jack V.
Santamauro Jon
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