Conditional precharge design in staticized dynamic flip-flop...

Details Conditional precharge design in staticized dynamic flip-flop... Conditional precharge design in staticized dynamic flip-flop...

2006-08-08

2006-08-08

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S093000, C326S094000, C326S095000, C326S096000, C326S097000, C326S098000, C326S112000, C326S121000

Reexamination Certificate

active

07088144

ABSTRACT:
A method and apparatus for creating a modified dynamic flip-flop avoids the power waste created by prior art dynamic flip-flops by including a conditional pre-charge control circuit and method. When the modified dynamic flip-flop is in a holding mode, i.e., in the clock disable state, the modified dynamic flip-flop does not use power pre-charging and discharging the internal dynamic node every cycle.

REFERENCES:
patent: 5898330 (1999-04-01), Klass
patent: 6222404 (2001-04-01), Mehta et al.
patent: 6424195 (2002-07-01), Samala
patent: 6429689 (2002-08-01), Allen et al.
patent: 6646487 (2003-11-01), Nedovic et al.
patent: 6654893 (2003-11-01), Samala
patent: 6879186 (2005-04-01), Liu

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