Conditional latch circuit

Details Conditional latch circuit Conditional latch circuit

1976-08-02

1977-04-19

Miller, Jr., Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307218, 307216, 307289, 328206, H03K 1904, H03K 312

Patent

active

040191443

ABSTRACT:
A conditional latch circuit is selectively operable as a latch or as an OR gate. The circuit comprises an OR gate having at least three inputs, each connected to the output of separate ones of three AND gates. A fourth AND gate has an inverted output connected to an input of two AND gates and a non-inverted output connected to an input of the third AND gate. The output of the OR gate is connected to a second input of the third AND gate. With one input of the fourth AND gate connected to a binary clock source, the circuit will operate as a latch to store binary signals received at the second input of the first and second AND gates when the second input of the fourth AND gate is connected to binary one. When the second input of the fourth AND gate is connected to a binary zero, the circuit will operate as an OR circuit.

REFERENCES:
patent: 3226569 (1965-12-01), James
patent: 3339089 (1967-08-01), Bergman
patent: 3339145 (1967-08-01), MacSorley
patent: 3588545 (1971-06-01), Wright
patent: 3679915 (1972-07-01), Kriger
patent: 3751683 (1973-08-01), Drost
patent: 3882325 (1975-05-01), Sakalay

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