Conditional clock gate that reduces data dependent loading...

Details Conditional clock gate that reduces data dependent loading... Conditional clock gate that reduces data dependent loading...

2001-07-31

2003-03-04

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S095000, C326S098000, C327S211000, C327S212000

Reexamination Certificate

active

06529044

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to clock generation in an integrated circuit. More particularly, the present invention relates to conditional clock gates that are used in integrated circuits to reduce power dissipation. Still more particularly, the present invention relates to a conditional clock gate that more effectively isolates the clock signal from the enable signal to reduce loading.
2. Background of the Invention
One of the critical design elements in modem processor chips and other large scale integrated circuits is the distribution of clock signals within the integrated circuit. Most digital circuits require a clock signal to operate, and data in a digital circuit typically is latched, processed, and output on one or more edges (i.e., the rising edge, the falling edge, or both) of the clock signal. Thus, without a good quality clock signal, most digital circuits will not operate properly, or will operate erratically.
In modem processor designs, and other large scale integrated circuits, the clock signal may be distributed to relatively large areas. To enable the clock signal to be effectively transmitted over long distances, it is common to use a clock distribution network to distribute the clock signal to all digital circuits within the integrated circuit die. The generation and transmission of the clock signal to the various digital circuitry on the die consumes a significant amount of power. In some instances, the integrated circuit may be designed to minimize the amount of power consumed by the integrated circuit during normal operation. As an example, it is desirable to design low power integrated circuits for systems that operate from battery power. Thus, processors intended for use in notebook computers or personal device assistants (PDAs) often are designed to minimize power consumption when the device is in a low power mode.
One common technique to minimize power consumption in integrated circuits is to turn off or disable the clock signal for circuits that are not being used. For example, it may be desirable in a processor to disable the clock signal to certain banks of a data cache if those banks are dormant. Consequently, it has become common to place conditional clock gates in the clock distribution network to enable certain clock branches to be disabled for power conservation.
A conditional clock (which also is referred to as a gated clock) typically is implemented as a two-input NAND gate or NOR gate, where the clock signal comprises one input, and an enable signal comprises the second input. The enable signal thus determines if the clock signal will be passed through the conditional clock gate. Examples of a conditional NAND gate are shown in
FIGS. 1A and 1B
, and a conditional NOR gate is depicted in
FIGS. 2A and 2B
. One of the problems with these conditional clock gates is that they introduce some data-dependent loading on the clock network due to the change of state of the enable input signal. This loading on the clock signal can cause jitter (or non-uniformity) in the clock signal. Clock jitter may be manifested by a change in phase, amplitude, or both, of the clock signal. Clock jitter maybe caused by a change in capacitance across clock transistor gates due to a change in state of the enable signal. This problem will be described in more detail by referring to the NAND conditional gate of Figure IA.
When the enable signal in Figure IA is held high (a logical “1”), the enable nFET conducts while the enable pFET is non-conducting. When the clock signal is high (a “1”), the clocked pFET is non-conducting, while the clocked nFET conducts. Because both the enable nFET and the clocked nFET are conducting, the output terminal of the NAND gate is pulled low (i.e., a “0”) by V
SS
. As the clock input signal goes low, the clocked nFET becomes non-conducting, while the clocked pFET becomes conducting. This places a charge (i.e., a “1”) on the output terminal. During the time that the clock signal is high, the source and drain of the enable pFET are at substantially the same voltage level, and this voltage level changes inversely with the clock signal voltage.
When the enable signal is low (i.e., a “0”), the enable nFET is non-conductive, while the enable pFET conducts. The enable pFET places a charge (i.e., a “1”) on the output terminal, producing a continuous high signal at the output of the NAND gate. Even though the output terminal of the NAND gate is driven high while the enable signal is low, the clock signal continues to run, which turns on and off the clocked nFET and clocked pFET gates. In particular, when the clock signal is low, the clocked nFET is non-conducting, while the clocked pFET is conducting. This places a high voltage level on the drain terminal of the non-conducting enable nFET. When the clock transitions to a high voltage level, the clocked pFET becomes non-conducting, while the clocked nFET turns on. The clocked nFET pulls the source of the non-conducting enable pFET low. After the initial clock cycle, and as long as the enable signal remains low, a high voltage level (a “1”) is maintained at the drain terminal of the enable nFET, while a low voltage level (a “0”) is maintained on the source terminal of the enable pFET. As a result, the clocked nFET will have a low voltage at both its source and drain terminals when the enable signal is low (after the first clock cycle). By comparison, and as noted above, when the enable signal is high, on every other cycle the clocked nFET has a high voltage at its drain terminal. The net effect is that the clocked nFET will have a different load (or a different capacitance between the source and drain terminals) depending on whether the enable signal is high or low.
The different loading on the clocked transistor gates can affect the characteristics of the clock signals that propagate on the clock distribution network, and thus can affect the manner in which the digital circuitry operates. Thus, the varying load encountered by the clock signal due to the varying nature of the enable signal can result in operational abnormalities. As one skilled in the art will appreciate, similar variances in clock load also are present in the NAND conditional clock gate of
FIG. 1A
, and in the NOR conditional clock gates depicted in
FIGS. 2A and 2B
.
To minimize clock jitter, it would be advantageous if the clock load (or the capacitance) were more constant, regardless of the state of the enable signal. Maintaining a constant load on the clocked transistor gates would reduce jitter, and thereby improve the quality of the clock signal. Despite the apparent advantages of presenting a constant load to the clocked gates, to date no one has developed a design that solves the problem with loading that results from a change in the state of an enable signal in a conditional clock gate.
BRIEF SUMMARY OF THE INVENTION
The present invention solves the deficiencies of the prior art by implementing a conditional clock gate that minimizes data loading caused by a change in state of the enable signal. According to the preferred embodiment, the conditional clock gate is configured to produce a pre-charge (or pre-discharge) on the transistor stack that is used to implement the NAND or NOR conditional clock gate. This pre-charge (or pre-discharge) produces a uniform load in the transistor stack, which eliminates clock jitter, and produces a better synchronized clock signal.
According to one embodiment of the present invention, a pre-charge transistor is used to charge the drain terminal of a clocked nFET gate when the clock input signal is low, and during periods when an enable signal input is de-asserted. In another embodiment, a pre-discharge transistor may be used to discharge the drain of a clocked pFET gate when the clock signal is high, and during periods when the enable signal is de-asserted. The present invention can also be

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