Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2001-06-28
2004-09-14
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S016000
Reexamination Certificate
active
06791364
ABSTRACT:
FIELD
Embodiments of the present invention relate to digital circuits, and more particularly, to dynamic circuits.
BACKGROUND
The functionality and reliability of microprocessors are usually tested under conditions that are relatively extreme when compared to normal operating conditions. During testing, the temperature and supply voltage may exceed the upper bounds of their respective target operating ranges. This is often referred to as burn-in or stress testing.
The burn-in process may set a severe constraint on dynamic circuits, requiring relatively large keepers during burn-in to compensate for additional leakage currents due to the higher temperature and supply voltage. Leakage currents are relatively small currents present when a transistor is not fully turned ON, e.g., when the magnitude of the gate-to-source voltage is less than the transistor's threshold voltage. Leakage current may present more of a design problem as transistor sizes are made smaller. Although larger keepers may meet the burn-in condition while compensating for leakage currents in the dynamic circuit, they nevertheless would be oversized for normal operating conditions. Using larger keepers during normal operating conditions may degrade microprocessor performance.
The prior art circuit of
FIG. 1
provides a conditional keeper for burn-in, and a normally sized keeper during normal operation, so that the burn-in conditions are met without degrading the performance of the microprocessor during normal operation. See D. Stasiak, et al., “A 2
nd
Generation 440 ps SOI 64b Adder,” ISSCC 2000, pp. 288-289.
For simplicity, only one stage of a dynamic circuit is shown in FIG.
1
. Network
102
represents a plurality of nMOSFETs (Metal Oxide Semiconductor Field Effect Transistor) configured to conditionally pull node
110
LOW during an evaluation phase so as to synthesize the particular logic function that is desired. During an evaluation phase, pMOSFET
104
is OFF, and during a pre-charge phase, pMOSFET
104
is ON to pull node
110
HIGH. Network
102
in general will have a plurality of input ports for receiving digital voltages, perhaps from other stages in the dynamic circuit.
Inverter
106
and pMOSFET
108
are configured as a keeper (or half-keeper), so that during an evaluation phase node
110
is kept HIGH if network
102
does not pull node
110
LOW. Static CMOS (Complementary Metal Oxide Semiconductor)
116
may be a static inverter or other logic gate, whose output may be provided to another stage of the dynamic circuit.
Inverter
106
and pMOSFET
108
are sized for normal operating conditions. The two stacked pMOSFETs
112
and
114
, together with inverter
106
, comprise what may be referred to as a conditional keeper for burn-in testing. pMOSFETs
112
and
114
are sized appropriately for the operating conditions of a burn-in test. The gate of pMOSFET
114
is activated by a signal BI-active (Burn-In active), where BI-active is set HIGH when the microprocessor is operating normally, and is set LOW during a burn-in test. With BI-active set LOW, pMOSFET
114
is ON, and inverter
106
, together with pMOSFETs
112
and
114
, act as a keeper, properly sized for the burn-in conditions.
Stacking MOSFETs, i.e., connecting the drain of one to the source of the other, reduces their overall effective gain. Because pMOSFETs
112
and
114
are in a stacked configuration, they should be sized up approximately twice as large as compared for a single, non-stacked pMOSFET keeper in order to compensate for the reduced gain. However, sizing up pMOSFETs
112
and
114
may have some disadvantages. Sizing up pMOSFETs
112
and
114
uses a larger chip (die) area. Also, the larger size increases the load on inverter
106
, which may degrade the response of pMOSFET
108
when performing its standard keeper operation during normal operation conditions. As a result, inverter
106
may also need to be sized larger, which in turn increases the load on node
110
, which may result in an increase in switching power and delay of the dynamic gate.
REFERENCES:
patent: 4549101 (1985-10-01), Sood
patent: 5467026 (1995-11-01), Arnold
patent: 6002292 (1999-12-01), Allen et al.
WA 17.1 A 2ndGeneration 440ps SOL 64b Adder, 2000 IEEE International Solid Circuites Conference pp. 288-289.
Alvandpour Atila
Krishnamurthy Ram K.
Chang Daniel
Intel Corporation
Kalson Seth Z.
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