Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2002-05-30
2010-12-28
Petranek, Jacob (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S022000
Reexamination Certificate
active
07861071
ABSTRACT:
A method of conditionally executing branch instructions which comprise an opcode field defining a type of test to be applied to determine whether or not to execute a branch operation, a control field designating a control store holding a plurality of indicators and a destination field holding information on a branch target address. The method comprises determining from the opcode field whether or not the test will check the state of one indicator or a plurality of indicators in the designated control store, accessing the designated control store to check the state of said one or said plurality of indicators depending on the determination, and generating a branch target address using information in the destination field in dependence on the state of the or each indicator checked.
REFERENCES:
patent: 3325785 (1967-06-01), Stevens
patent: 3958227 (1976-05-01), Evans
patent: 4589065 (1986-05-01), Auslander et al.
patent: 4589087 (1986-05-01), Auslander et al.
patent: 4748585 (1988-05-01), Chiarulli et al.
patent: 5056015 (1991-10-01), Baldwin et al.
patent: 5471593 (1995-11-01), Branigin
patent: 5530825 (1996-06-01), Black et al.
patent: 5542084 (1996-07-01), Lowe, Jr.
patent: 5555428 (1996-09-01), Radigan et al.
patent: 5568631 (1996-10-01), Webb
patent: 5615386 (1997-03-01), Amerson et al.
patent: 5838984 (1998-11-01), Nguyen et al.
patent: 5996070 (1999-11-01), Yamada et al.
patent: 6041399 (2000-03-01), Terada et al.
patent: 6052776 (2000-04-01), Miki et al.
patent: 6240510 (2001-05-01), Yeh et al.
patent: 6282628 (2001-08-01), Dubey et al.
patent: 6298438 (2001-10-01), Thayer et al.
patent: 6336178 (2002-01-01), Favor
patent: 6338137 (2002-01-01), Shiell et al.
patent: 6366999 (2002-04-01), Drabenstott et al.
patent: 6478521 (2002-11-01), Tschunko et al.
patent: 6484255 (2002-11-01), Dulong
patent: 6513109 (2003-01-01), Gschwind et al.
patent: 6622238 (2003-09-01), Benjamin et al.
patent: 6675291 (2004-01-01), Benayoun et al.
patent: 6676291 (2004-01-01), Ahn
patent: 6748521 (2004-06-01), Hoyle
patent: 6757819 (2004-06-01), Hoyle et al.
patent: 6772325 (2004-08-01), Irie et al.
patent: 6986025 (2006-01-01), Wilson
patent: 7017032 (2006-03-01), Wilson
patent: 7127593 (2006-10-01), Wilson
patent: 2001/0042190 (2001-11-01), Tremblay et al.
patent: 2006/0149953 (2006-07-01), Wilson
patent: 0 130 381 (1985-01-01), None
patent: 0130381 (1985-01-01), None
patent: 0 395 348 (1990-10-01), None
patent: 0 627 681 (1994-12-01), None
patent: 1 089 170 (2001-04-01), None
patent: 1089170 (2001-04-01), None
patent: WO 01/06353 (2001-01-01), None
Heinrich, Joe. MIPS R4000 Microprocessor User's Manual, 2nded. 1994. p. A-33.
Hennessy and Patterson. Computer Organization and Deisgn, 2nded. Morgan kaufmann Publishers, Inc. 1998. pp. 384, 386 and 387.
Intel Architecture Software Developer's Manual, 1997. vol. 1: Basic Architecture, pp. 3-10 to 3-12, 6-23 , 6-31 to 6-33, A-1 to A-4 and B-1 to B-2, and vol. 2, Instruction Set Reference, pp. 3-241 to 3-243.
The PowerPC Architecture: A Specification for a New Family of RISC Processors. Morgan Kaufmann Publishers, Inc., 1994. pp. 36-37.
International Search Report issued Mar. 19, 2003 for Appln. No. EP 02 25 4001, 3 pages.
Lee, Ruby B., “Subword Parallelism With MAX-2”IEEE Inc., vol. 16, No. 4, 1996.
International Search Report issued Mar. 19, 2003 for Appl. No. EP 02 25 4002, 3 pages.
International Search Report issued Mar. 19, 2003 for Appl. No. EP 02 25 4000, 3 pages.
Final Rejection mailed Nov. 12, 2009 for U.S. Appl. No. 11/373,198, 8 pgs.
Non-Final Rejection mailed Apr. 3, 2009 for U.S. Appl. No. 11/373,198, 8 pgs.
Final Rejection mailed Sep. 15, 2008 for U.S. Appl. No. 11/373,198, 8 pgs.
Broadcom Corporation
Petranek Jacob
Sterne Kessler Goldstein & Fox PLLC
LandOfFree
Conditional branch instruction capable of testing a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Conditional branch instruction capable of testing a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Conditional branch instruction capable of testing a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4192978