Condition code stack architecture systems and methods

Details Condition code stack architecture systems and methods Condition code stack architecture systems and methods

1999-08-10

2003-06-03

Lee, Thomas (Department: 2185)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S233000, C712S226000

Reexamination Certificate

active

06574728

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This application relates to computers and computer operations, and more particularly to condition code stack architecture systems and methods used in computer systems.
2. Description of Related Art
The related art includes U.S. Pat. No. 5,517,628 “Computer with Instructions that Use an Address Field to Select Among Multiple Condition Code Registers,” granted to Gordon E. Morrison, Christopher B. Brooks, and Frederick G. Gluck of Biax Corporation, on May 14, 1996. As described in the '628 patent, condition code register files are distinct from a computer's general purpose register file. The condition code register file has a plurality of addressable condition code registers. The computer executes condition-setting instructions that produce condition code values for storage in condition code registers. Conditional branch instructions branch to a target based upon analysis of a condition code value from one of the condition code registers. The condition code registers are directly addressable by condition code address fields of the instructions. The contextual information of the condition code registers is stored as bits associated with the respective processor elements. These bits are used for branching and are the result of executing certain comparison and test instructions. In the '628 patent, the processor has multiple sets of condition code registers. The processor's arithmetic and logical operations alter a condition code register state, and that state is available even after execution of other arithmetic and logical operations. Further, the processor's control transfer operations can specify which of the condition code registers is to be the basis for a jump. Unfortunately, use of a register file of condition codes requires complex management software, such as compiler software for example. This software is needed to manage which of the sets of condition codes will be used in each instruction. Additionally, the '628 patent requires excessive bit processing in arithmetic, logical, and control transfer instructions to specify the identity of the required condition code register to be used with the applicable instruction. This consumes excessive instruction code space.
SUMMARY OF THE INVENTION
According to one embodiment of the present invention, a program status word in a computer system architecture includes condition codes stored in a selfmanaging stack which does not require management or compiler software for operational enablement. According to the present invention, predetermined bits in a control transfer instruction such as a conditional jump instruction identify the applicable condition code register to be used with a control transfer instruction. However, no bits need to be identified for arithmetic and logical instructions for use with the particular instructions, thereby saving considerable instruction code space. According to another embodiment of the present invention, a computer system includes a register file and an arithmetic logic unit (ALU) for reading data from said register file, and storing the results of processing read data in said register file, as well as storing in a condition code stack context data indicative of the results of data processing by said processor. The ALU is configured to query the condition code stack for predetermined bit values to determine operations controlled by the ALU.


REFERENCES:
patent: 3577189 (1971-05-01), Cocke et al.
patent: 5125092 (1992-06-01), Prener
patent: 5193157 (1993-03-01), Barbour et al.
patent: 5517628 (1996-05-01), Morrison et al.
patent: 5659722 (1997-08-01), Blanner et al.
patent: 5689695 (1997-11-01), Read
patent: 5991868 (1999-11-01), Kamiyama et al.
patent: 6052776 (2000-04-01), Miki et al.
IBM Technical Disclosure Bulletin, Jul. 1988; IBM, NN8807294, “Multiple Queued Condition Codes”, vol. 31, Issue No. 2, pp 294-296.*
Hammacher, Vranesic, Zaky, “Computer Organization”, Copyright 1984, McGraw-Hill, Inc, ISBN 0-07-025683-7, pp. 27-30.

Affiliated with

Also associated with

Rating

Condition code stack architecture systems and methods does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Condition code stack architecture systems and methods, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Condition code stack architecture systems and methods will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3121127