Concurrent refresh mode with distributed row address...

Details Concurrent refresh mode with distributed row address... Concurrent refresh mode with distributed row address...

2005-11-22

2005-11-22

Mai, Son (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189040, C365S230030

Reexamination Certificate

active

06967885

ABSTRACT:
A concurrent refresh mode is realized by allowing a memory array to be refreshed by way of a refresh bank select signal, while concurrently enabling a memory access operation in another array. The refresh address management is greatly simplified by the insertion of row address counter integrated within each array. In the preferred embodiment, any combination of a plurality of the memory arrays is refreshed simultaneously while enabling a memory access operation. This concurrent mode also supports a multi-bank operation.

REFERENCES:
patent: 5555527 (1996-09-01), Kotani et al.
patent: 6563757 (2003-05-01), Agata
patent: 6819617 (2004-11-01), Hwang et al.

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