Concurrent measurement of critical dimension and overlay in...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

07080330

ABSTRACT:
A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. One or more structures formed on a wafer matriculating through the process facilitate concurrent measurement of critical dimensions and overlay via scatterometry or a scanning electron microscope (SEM). The concurrent measurements mitigate fabrication inefficiencies, thereby reducing time and real estate required for the fabrication process. The measurements can be utilized to generate feedback and/or feed-forward data to selectively control one or more fabrication components and/or operating parameters associated therewith to achieve desired critical dimensions and to mitigate overlay error.

REFERENCES:
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patent: 2002/0018217 (2002-02-01), Weber-Grabau et al.
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Kynett et al.,“A in-system reprogrammable 32 K×8 CMOS Flash Memory”, Oct. 1988, IEEE Jpurnal of Solid-State Circuits, vol. 23, iss. 5, pp. 1157-1163.

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