Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-11-15
2004-09-14
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C326S038000
Reexamination Certificate
active
06792582
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention generally relates to computer-aided placement of circuits on a semiconductor chip, and more specifically relates to concurrent logical and physical construction of voltage islands for mixed supply voltage designs.
2. Background Art
The switching power of digital circuits increases as the square of the power supply voltage increases. Thus, reducing this voltage is desirable for reduction in circuit power consumption. However, reduction in power supply voltage also reduces circuit performance. Therefore, it is desirable to combine circuits driven by a higher power supply voltage and circuits driven by a lower power supply voltage (hereafter referred to as high and low voltage circuits, respectively) on the same chip. The high voltage circuits are used where needed to achieve the desired circuit performance and the low voltage circuits are used elsewhere.
When high and low voltage circuits are combined on a semiconductor chip in this way, it is desirable to physically group the low voltage circuits together in low voltage “islands” and to separately group the high voltage circuits together into high voltage “islands”. This is preferable because the high and low voltage power supplies are distributed on separate distribution networks and, by grouping the circuits into islands, only one of the two power supplies needs to be distributed within each island. This reduces the amount of extra wiring resource required to distribute the two power supplies, thereby leaving more wiring resource available for signal wiring. Ultimately, this allows the semiconductor chip to be smaller and/or fewer wiring planes to be required.
When high and low voltage circuits are combined on a chip, care must also be taken for nets that are driving signals from one type of circuit to the other. Typically, high voltage circuits can directly drive low voltage circuits with no special intervening circuitry, but low voltage circuits feeding high voltage circuits must drive them through special “level-shifter” circuits. Such circuits add area, power, and delay to the network. Therefore, it is desirable to minimize their use. In many circuit families, high voltage latch circuits can act as level shifters at no additional cost. Thus, if low voltage circuits are selected so that they directly feed latches, the number of level-shifters needed can be reduced. The number of level-shifters needed is typically reduced by assigning groups of closely connected circuits to high or low voltage.
In summary, placing high voltage circuits in high voltage islands and low voltage circuits in low voltage islands typically minimizes the number of level shifters used. This also reduces the number of places to which the high and low voltage power must route, thereby reducing power distribution costs. However, these islands may not be conducive to good logical placement. For example, a signal might have to run quite a long distance to a high voltage island and then from the high voltage island back to circuitry that uses this signal. This could actually decrease performance instead of increasing it. Thus, a poor placement result occurs for what should be a better placement.
Another method used for creating high and low voltage circuits is logical clustering. In logical cluster, the high and low voltage circuits are designed—not in voltage islands—based on connectivity. Elements in a circuit that need to be faster are changed to higher voltage, while slower, non-critical elements are changed to lower voltage. This solves the placement issues caused by high and low voltage island clustering, as the data paths are not moved. However, the different power supplies must be distributed everywhere and logical clustering can tremendously increase the number of level shifters.
Thus, there is a need to limit the amount of power routing and level shifters, yet still allow critical data paths to meet timing requirements.
DISCLOSURE OF THE INVENTION
The preferred embodiments of the present invention solve these problems by providing both logical and physical construction of voltage islands. The preferred embodiments of the present invention combine both physical and logical synthesis to provide fewer level shifters and less power routing, but still meet timing and other requirements. Additionally, by using an iterative process for construction of the voltage islands, power usage can be minimized while speed constraints, in particular, are met.
In one aspect of the present invention, a semiconductor chip design is partitioned into “bins”, which are areas of the design. In this way, a semiconductor chip design may be “sliced” into various areas and the areas may then be assigned to various voltage levels. Each bin may be thought of as a voltage island. Circuits in the design can be added to or removed from the various bins, thereby increasing or decreasing the speed and power of the circuits: the speed and power increase if a circuit is placed into a bin assigned a higher voltage, and the speed and power decrease if a circuit is placed into a bin having a lower voltage. The size and location of the bins may also be changed. By iterating these steps, the optimum power consumption may be met while still meeting speed constraints and other criteria.
Thus, instead of solely adding circuits to a voltage island, or solely determining which circuits need higher voltage and changing these circuits to higher voltage levels, the present invention combines these two concepts. The present invention uses both physical and logical construction of voltage islands to meet predetermined criteria.
Dividing a semiconductor chip design into a number of bins is only one way of placing circuits in a design. The present invention is applicable to any placement environment that proceeds through successive refinement of the locations of the circuits on the design and in which the placement process may be interrupted to make changes in placement of the logic.
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Cohn John M
Dean Alvar A.
Hathaway David J.
Lackey David E.
Lepsic Thomas M.
International Business Machines - Corporation
Kotulak Richard M.
Thompson A. M.
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