Concurrent execution of divide microinstructions in floating poi

Details Concurrent execution of divide microinstructions in floating poi Concurrent execution of divide microinstructions in floating poi

1998-07-01

2000-05-09

Kim, Kenneth S.

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

708552, 708650, 708655, G06F 752

Patent

active

060617810

ABSTRACT:
An apparatus and method for performing integer division in a microprocessor are provided. The apparatus includes translation logic, floating point execution logic, and integer execution logic. The translation logic decodes an integer divide instruction into an integer divide micro instruction sequence and an overflow detection micro instruction sequence. The integer divide micro instruction sequence is routed to and executed by the floating point execution logic. The overflow detection micro instruction sequence is routed to and executed by the integer execution logic. The integer execution logic and the floating point execution logic execute the overflow detection micro instruction sequence and the integer divide micro instruction sequence concurrently.

REFERENCES:
patent: 4992969 (1991-02-01), Yamahata
patent: 5272660 (1993-12-01), Rossbach

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