Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-08-19
2001-02-13
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S308000, C257S310000, C257S295000, C257S296000
Reexamination Certificate
active
06188100
ABSTRACT:
FIELD OF INVENTION
The invention relates generally to integrated circuits and more particularly to a finned capacitor for use in an integrated circuit.
BACKGROUND OF THE INVENTION
Capacitors are used in a wide variety of semiconductor circuits. Capacitors are of special concern in DRAM (dynamic random access memory) memory circuits; therefore, the invention will be discussed in connection with DRAM memory circuits. However, the invention has broader applicability and is not limited to DRAM memory circuits. It may be used in any other type of memory circuit, such as an SRAM (static random access memory), as well as in any other circuit in which capacitors are used.
The manufacturing of a DRAM cell includes the fabrication of a transistor, a capacitor, and three contacts: one each to the bit line, the word line, and the reference voltage. DRAM manufacturing is a highly competitive business. There is continuous pressure to decrease the size of individual cells and increase memory cell density to allow more memory to be squeezed onto a single memory chip. However, it is necessary to maintain a sufficiently high storage capacitance to maintain a charge at the refresh rates currently in use even as cell size continues to shrink. This requirement has led DRAM manufacturers to turn to three dimensional capacitor designs, including trench and stacked capacitors. Stacked capacitors are capacitors which are stacked, or placed, over the access transistor in a semiconductor device. In contrast, trench capacitors are formed in the wafer substrate beneath the transistor. For reasons including ease of fabrication and increased capacitance, most manufacturers of DRAMs larger than 4 Megabits use stacked capacitors. Therefore, the invention will be discussed in connection with stacked capacitors but should not be understood to be limited thereto. For example, use of the invention in trench capacitors is also possible.
One widely used type of stacked capacitor is known as a container capacitor. Known container capacitors are in the shape of an upstanding tube (cylinder) having an oval or circular cross section.
FIG. 1
illustrates a top view of a portion of a DRAM memory circuit from which the upper layers have been removed to reveal container capacitors
14
arranged around a bit line contact
16
. Six container capacitors
14
are shown in
FIG. 1
, each of which has been labeled with separate reference designations A to F. In
FIG. 1
, the bit line contact
16
is shared by DRAM cells corresponding to container capacitors A and B. The wall of each tube consists of two plates of conductive material such as doped polycrystalline silicon (referred to herein as polysilicon or poly) separated by a dielectric. The bottom end of the tube is closed, with the outer wall in contact with either the drain of the access transistor or a plug which itself is in contact with the drain. The other end of the tube is open (the tube is filled with an insulative material later in the fabrication process). The sidewall and closed end of the tube form a container; hence the name “container capacitor.” Although the invention will be further discussed in connection with stacked container capacitors, the invention should not be understood to be limited thereto.
As memory cell density continues to increase, there is needed a capacitor that has an increased effective capacitance per cell. The present invention provides a fabrication process and capacitor structure that achieves high storage capacitance without increasing the size of the capacitor or requiring complex fabrication steps.
SUMMARY OF THE INVENTION
The present invention provides a three-dimensional capacitor cell which maintains high storage capacitance without increasing cell area. The capacitor cell of the present invention includes a container capacitor having a concentrically formed internal fin as shown, for example, in FIG.
2
B. The fabrication process is advantageous in its simplicity, requiring only two additional deposition steps, a spacer etch and a wet etch.
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patent: 5534458 (1996-07-01), Okudaira et al.
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patent: 5729054 (1998-03-01), Summerfelt et al.
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Dickstein , Shapiro, Morin & Oshinsky, LLP
Fenty Jesse A.
Micro)n Technology, Inc.
Saadat Mahshid
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