Concave channel MOS transistor and method of fabricating the sam

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257332, 257335, 257401, 257408, 257412, 257622, 437 40, 437 44, 437228, 437233, 437235, H01L 2968, H01L 21265

Patent

active

054480949

ABSTRACT:
A MOS transistor with concave channel and method of fabrication is provided. First, a LOCOS procedure is performed to form a field oxide layer on a silicon substrate by using a barrier layer as a mask. Next, the field oxide is removed to leave a concave area in the silicon substrate. Silicon dioxide sidewall spacers are formed apart on side walls of the barrier layer. A gate oxide layer is formed on the bottom of the concave area. A polysilicon layer is formed in conformity with the exposed surfaces of the barrier layer, the silicon dioxide sidewall spacers, and the gate oxide layer. A mask layer is formed overlying the polysilicon layer within the concave area. Then, portions of the polysilicon layer not covered by the mask layer are removed, so that the remained portion of the polysilicon layer and the gate oxide layer together construct a gate electrode, while the area under the gate electrode forms a concave channel. The mask layer and the barrier layer are removed respectively. Heavily doped source/drain areas are formed by a first ion implantation using the gate electrode and the silicon dioxide sidewall spacers as self-align masks. After removing the silicon dioxide sidewall spacers, lightly doped source/drain areas are formed by a second ion implantation using the gate electrode as a self-align mask.

REFERENCES:
patent: 5105242 (1992-04-01), Fujihiar et al.
patent: 5142640 (1992-08-01), Iwamatsu

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