Computing system accessible to a split line on border of two pag

Details Computing system accessible to a split line on border of two pag Computing system accessible to a split line on border of two pag

1997-11-06

1999-11-23

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

711123, 711201, 711207, 711219, G06F 1208

Patent

active

059918489

ABSTRACT:
This invention is developed to provide a computing system which can carry out a high speed access to a cache memory within one cycle even though data needed to be read is on the border of two pages. To realize the high speed computing system accessible to a split line on the border of two pages within one cycle, the computing system includes a translation lookaside buffer (TLB) which is designed to have a dual port structure, a prefetcher and a data/code cache memory which is improved for supporting the translated lookaside buffer (TLB).

REFERENCES:
patent: 5623619 (1997-04-01), Witt
patent: 5802576 (1998-09-01), Tzeng et al.

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