Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-04-29
2002-03-12
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06357036
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of computerized integrated circuit design, in particular a computerized method and apparatus for designing bond diagrams and locating bond pads for a semiconductor device.
BACKGROUND OF THE INVENTION
The design of integrated circuits is by and large a highly automated process. Complex and powerful software tools are available for converting a logic level design into a semiconductor circuit design ready to be etched and formed on a semiconductor substrate.
Such programs, such as those provided by Avant! Corporation of Fremont, Calif. and Cadence Design, of San Jose, Calif. automatically route conductors and locate components on a semiconductor chip using well established rules of design as well as huge libraries of pre-stored design modules. Once the design for a semiconductor circuit has been completed, the resultant design, in a standardized electronic format (e.g., Opus, GDSII, or the like) may be transmitted to a semiconductor fabrication facility or “fab” for fabrication.
However, fabrication represents only the circuit manufacturing portion of the semiconductor manufacturing process. Once circuits are formed on a semiconductor wafer, the wafer must then be broken into a number of discrete “chips” and mounted on a chip carrier with electrical leads wire-bonded from pads on the chip to conductors on the chip carrier.
Unlike the semiconductor design process, the process of designing the wire bonding layout has been largely manual. Engineers, using magnified copies of chip diagrams, resort to using rulers and pencils to draw in the locations of wire bonds. These drawn-in wire bond diagrams may then be used by an assembly facility to instruct a wire bonding machine as to which pad on a chip should be connected to which lead on the chip carrier. In some instances, not all pads may be bonded, and some leads may be bonded to more than one pad. Correct and accurate bonding information is essential to proper manufacturing of the completed circuit.
However, such hand-drawn circuit diagrams do not lend themselves well to automated processing. Moreover, pencilled-in diagrams may not photocopy properly, with the result that one or more bonds may be missed or incorrectly formed. In addition, with the ever increasing number of leads used in semiconductor devices (e.g., 128 or more), hand-drawing of such bonds maybe cumbersome and error prone.
When drawing such bonds on a bonding diagram, the Engineer also uses this opportunity to insure that the bonds comply with certain predetermined design criteria. For example, bonds which are too long may tend to sag when encapsulated, shorting out with adjacent bonds or the chip edge. Similarly, bonds may be required to be formed only within a certain angle from the chip or at a certain distance from adjacent bonds, to prevent mechanical or electrical interference.
Manually drawing and measuring such bonds may be a tedious and inaccurate process. Using a scaled-up drawing, the Engineer must be sure to make careful measurements with a rule to insure bonds are within design criteria.
In addition, if one or more bonds are not within design criteria, the Engineer must move a bonding pad in the chip design in order to correct the error. Such a move may require that the chip design be manually altered through manipulation of the semiconductor circuit design program.
Schweiss, U.S. Pat. No. 5,155,065, issued Oct. 13, 1993, discloses a method for configuring a plurality of pads on a semiconductor die to accommodate more than one pad pitch. Pad sizes and pad spacings are adjusted to achieve the pad configuration, which may form a pattern. This pattern may be repeated to meet the number of pads needed in the application. Schweiss is cited here as background only in that it teaches various techniques for determining correct pad spacing and pitch.
Tain et al., U.S. Pat. No. 5,608,638, issued Mar. 4, 1997, discloses a device and method for automation of a build sheet to manufacture a packaged integrated circuit. Tain et al. uses a GUI program to allow an engineer to generate buildsheet data automatically. This buildsheet data appears to include die size, wire bonding and die image. It appears that the “build sheet” is directed toward a wire bonding diagram.
However, Tain et al. does not make reference to making automated corrections to bond pad location nor package lead layouts for quality and yield optimization. Moreover, Tain et al., limited to a GUI application, makes no reference to operating system independence (i.e., Windows™ 95/98, NT or UNIX). In addition, Tain et al., makes no reference to techniques to keep file size at a minimum, transferability through gateways, networks, or FTP sites, or towards portability of a soft file to wire bond equipment to replace manual teaching techniques.
Huddleston et. al, U.S. Pat. No. 5,498,767, issued Mar. 12, 1996, discloses a method for positioning bond pads in a semiconductor die layout. Huddleston et al. teaches locating bond pads centers in account with both manufacturing and design limitations.
However, Huddleston et al. focuses only on determining wiring angle for silicon-to-package compatibility, and does not go beyond wire angle related issues. Thus, for Example, Huddleston et al. does not teach determining die size to die attach pad compatibility, minimum and maximum restrictions to wire length over silicon, over lead tip and overall bond length.
Yip, et al., U.S. Pat. No. 5,465,217, issued Nov. 7, 1995, also discloses an automated system for routing tape automated bonding (TAB) leads.
However, Yip et al. focusses on artwork for tape tab development based upon a desired pad pitch. The Yip et al. technique is thus restricted to tab based packages and does not encompass any semiconductor packaging and technologies for housing silicon (e.g., quad packages, dual-in-line packages, small outline packages, and the like).
Thus, it remains a requirement in the art to provide an automated process for designing bonding diagrams for semiconductor devices.
It remains a further requirement in the art to provide a technique for automatically determining whether a bonding layout complies with established bonding criteria.
It remains a further requirement in the art to provide a technique whereby a chip design may be automatically altered if one or more bonds do not meet established bonding criteria.
SUMMARY OF THE INVENTION
The present invention provides a bond tool utility software package which extracts bond pad location data from a semiconductor chip design stored in one of a number of known formats (e.g., Opus, GDSII, or the like) and extracts conductor location data from an AUTOCAD file of a chip frame design. The utility retrieves bonding connection data from a design ASCII file and generates a bonding diagram for the semiconductor assembly.
The utility also contains a subroutine for applying bonding design criteria to the resultant bonding diagram to determine whether all bonds are within established guidelines. If an impermissible bond is formed, the user may be alerted that one or more bonding pads may have to be relocated.
In one embodiment of the present invention, the bonding utility may interface with a semiconductor design circuit to generate a suggested fix to an impermissible bonding situation. One or more bonding pads may be moved in the semiconductor design to correct for potential bonding deficiencies.
REFERENCES:
patent: 4864514 (1989-09-01), Yamanaka
patent: 5155065 (1992-10-01), Schweiss
patent: 5465217 (1995-11-01), Yip et al.
patent: 5498767 (1996-03-01), Huddleston et al.
patent: 5608638 (1997-03-01), Tain et al.
patent: 5661669 (1997-08-01), Mozumder et al.
Eka Laiman
Fong Carl H.
Martinez, III Marcello R.
Bell Robert P.
Cirrus Logic Inc.
Do Thuan
Lin Steven
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