Computer with optimizing hardware for conditional hedge fetching

Details Computer with optimizing hardware for conditional hedge fetching Computer with optimizing hardware for conditional hedge fetching

1998-02-20

2000-03-07

Ellis, Richard L

Electrical computers and digital processing systems: processing

Processing control

Branching

712233, 712234, 712235, 712236, 712237, 712238, 712239, G06F 900

Patent

active

060353929

ABSTRACT:
A computer for executing programs and having a structure for fetching instructions and/or operands along a path which may not be taken by a process being executed by a computer processor having a hierarchical memory structure with data being loaded into cache lines of a cache in the structure, and having block line fetch signal selection logic and computational logic with hedge selection logic for generating line fetch block signals for control of hedging by fetching instructions and/or operands along a path which may not be taken by a process being executed and making selected hedge fetches sensitive to whether the data is in the cache so as to gain the best performance advantage with a selected hedge fetch signal which accompanies each fetch request to the cache to identify whether a line should be loaded if it misses the cache to indicate a selected hedge fetch when this signal is ON, and rejecting a fetch request in the event the selected hedge fetch signal is turned ON if the data is not in the cache, the cache will reject the fetch, and thereafter repeating the fetch request after a fetch request has been rejected when the selected hedge fetch signal was turned ON the data was not in the cache to repeat the fetch request at a later time when it is more certain that the process being executed wants the data, or never repeating the request upon determination that the process being executed does not need the data to he fetched.

REFERENCES:
patent: 4991080 (1991-02-01), Emma
patent: 5303356 (1994-04-01), Vassiliadis et al.
patent: 5353419 (1994-10-01), Touch et al.
patent: 5797020 (1998-08-01), Bonella
patent: 5809294 (1998-09-01), Ando
"Zero-Cycle Branches in Simple Risc Designs" IBM Technical Disclosure Bulletin, by Grohoski, vol. 33, No. 10B, Mar. 1991, p. 253-259.
"Architecting Computer System Locks" IBM Technical Disclosure Bulletin, by Liu, vol. 30, No. 9, Feb. 1988, p. 444-446.
"High-Speed Translation Mechanism" IBM Technical Disclosure Bulletin, by Weiss, vol. 25, No. 1, Jun. 1982, p. 59-61.
IBM, "Hedge Fetch History Table", IBM Tech. Disclosure Bulletin vol. 31, No. 9, pp. 101-202, Feb. 1989.

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