Computer with dynamic instruction reuse

Details Computer with dynamic instruction reuse Computer with dynamic instruction reuse

1997-06-13

1998-12-01

Treat, William M.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395376, 395381, 711133, 711137, G06F 930

Patent

active

058451030

ABSTRACT:
A computer architecture allowing reuse of previously determined instruction results, indexes instruction results according to instruction addresses. The continued validity of operand values in registers or memory for the instructions is determined prior to the fetching of any given instruction by an invalidation system which detects an intervening register or memory write. Thus, the need to evaluate the operand values themselves which would delay execution is avoided. In one embodiment, dependencies for operands between instructions are recorded so as to avoid invalidating instructions having operand register or memory locations which are overwritten when the overwriting will be corrected by an intervening instruction immediately preceding the dependent instructions.

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