Computer with cache-line buffers for storing prefetched data for

Details Computer with cache-line buffers for storing prefetched data for Computer with cache-line buffers for storing prefetched data for

1997-05-22

1999-10-26

Chan, Eddie P.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710107, 710113, 710116, 710119, 710128, 710 22, 710123, 710114, 710121, G06F 1300

Patent

active

059744979

ABSTRACT:
In a computer including two buses, a main memory, a write back cache, and a peripheral device, a method and apparatus for providing an inter-bus buffer to support successive main memory accesses from the peripheral device is disclosed. The buffer is included in a bridge device for interfacing the two computer buses and controlling when the peripheral device may access the main memory. When the peripheral device attempts to read data from the main memory that is duplicated in the cache and that has become stale, the bridge device initiates a write back operation to update specific data portions of the main memory corresponding to the read request. The bridge device uses look-ahead techniques such as bursting or pipelining to streamline the data coming from the cache to the main memory and to the peripheral device. When the peripheral device requests a misaligned memory read operation, upon termination of the read access due to preemption of the peripheral device, the cache line containing the remainder of the requested data is written back to the main memory, and stored in the buffler. The bridge device can then use the data stored in the buffer to respond to subsequent memory access requests from the peripheral device.

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