Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-10-29
2000-08-29
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 55, G06F 1100, H05K 1000
Patent
active
06112320&
ABSTRACT:
A watchdog timer for a computer with a CPU and a peripheral controller. The watchdog timer includes a program in the peripheral controller and a corresponding program in the peripheral interrupt service routine of the CPU. When the watchdog timer function is enabled, the peripheral controller will interrupt the CPU periodically and check the response from the CPU. If the CPU is not responding, or wrong data is returned from the CPU, the peripheral controller will generate a reset signal to reset the CPU and reboot the system.
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patent: 5233613 (1993-08-01), Allen et al.
patent: 5513319 (1996-04-01), Finch et al.
patent: 5850546 (1998-12-01), Kim
Beausoliel, Jr. Robert W.
Buchaca John D.
Charmasson Henri J. A.
Elisca Pierre Eddy
Jacobson William O.
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