Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Patent
1997-03-20
1999-11-02
Butler, Dennis M.
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
713600, G06F 104
Patent
active
059789298
ABSTRACT:
An integrated circuit such as a SRAM is connected to receive externally generated clock cycles. A delay period is generated within the circuit which is independent of the rate of the clock cycles. The rate of the clock cycles is compared to a delay period and the operation of the integrated circuit is varied depending on the comparison. The integrated circuit adapts itself to changes in operating temperature, applied voltages, process variations which result in structural or materials differences between devices, and changes in the rate of externally generated clock cycles.
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Covino Jim
Pilo Harold
Butler Dennis M.
International Business Machines - Corporation
Walsh Robert A.
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