Computer system with trigger controlled interface and method

Details Computer system with trigger controlled interface and method Computer system with trigger controlled interface and method

1997-12-29

2000-09-26

Auve, Glenn A.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

G06F 1300

Patent

active

061254134

ABSTRACT:
An interface (101) in a computer system has an port (150) which is coupled to a memory via a first bidirectional data path (104) and coupled to a peripheral device via a communication path (106). The interface (101) has a controller (170) with a trigger buffer (175) and a pointer register (160). The pointer register (160) provides a movable pointer (165) to memory entries of data queues. The trigger buffer (175) continuously receives and accumulates trigger signals (1 2 3) and sends start signals to the pointer register (165). A queue is transmitted through the first path (104), the port (150) and the second path (106) or vice versa when a first trigger (e.g., (1) signal arrives. The trigger buffer (175) receives further trigger signals (e.g., (2) and accumulates them in a trigger buffer (175) before it sends start signals (e.g., ) for further transmissions. Optionally, interface 101 provides start signals after prioritizing trigger signals.

REFERENCES:
patent: 4816996 (1989-03-01), Hill et al.
patent: 4958277 (1990-09-01), Hill et al.
patent: 5379379 (1995-01-01), Becker et al.
patent: 5805922 (1998-09-01), Sim et al.
"Queued Serial Module (QSM) Reference Manual" by Motorola, Inc. 1991, order No. QSMRM/AD.

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