Computer system with transparent processor sparing

Details Computer system with transparent processor sparing Computer system with transparent processor sparing

1998-04-30

2000-09-05

Le, Dieu-Minh T.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 13, 712227, 712228, H02H 305, H03K 19003, H04B 174

Patent

active

061158291

ABSTRACT:
A computer which has multiple central processing units where at least one of the processors is a spare and unused for normal system operation, provides a mechanism for transferring the micro-architected state of a checkstopped processor to a spare processor. Each processor has a set of registers in the central processing unit where the micro-architected state of the processor is kept and these registers are accessible by millicode or microcode running on that processor. A checkstop of a processor is detected by the system, the micro-architected state of that processor is extracted and returned to the system where that state can be loaded into a spare processor in the system and processing resumed without interruption.

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