Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1998-08-14
2001-06-19
Nguyen, Than (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C710S240000, C710S241000, C710S242000, C710S243000, C710S244000, C711S150000, C711S158000, C711S167000, C711S168000, C711S169000
Reexamination Certificate
active
06249847
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to computer systems and, more particularly, to memory controller designs for use in high performance computer systems. Still more particularly, the invention relates to the configuration and operation of an arbiter in a memory controller to permit some types of memory requests to be arbitrated synchronously while other types to be arbitrated asynchronously.
2. Background of the Invention
A personal computer system includes a number of components with specialized functions that cooperatively interact to produce the many effects available in modern computer systems. Early computer systems had relatively few components. As an example, some of the early computer systems included a processor (or CPU), random access memory (RAM), and certain peripheral devices such as a floppy drive, a keyboard and a display. These components typically were coupled together using a network of address, data and control lines, commonly referred to as a “bus.”
As computer technology evolved, it became common to connect additional peripheral devices to the computer to provide additional functionality.
FIG. 1
shows a representative prior art computer system that includes a CPU coupled to a bridge logic device via a CPU bus. The bridge logic device is sometimes referred to as a “North bridge” for no other reason than it often is depicted at the upper end of a computer system drawing. The North bridge also couples to the main memory array by a memory bus. The North bridge couples the CPU and memory to the peripheral devices in the system through a PCI bus or other expansion bus (such as an EISA bus). The North bridge interconnects and controls the flow of information between the CPU, the memory, the PCI bus, and other buses and devices as desired. Various components that understand PCI protocol may reside on the PCI bus, such as a graphics controller.
If other expansion busses are provided in the computer system, another bridge logic device typically is used to couple the PCI bus to that expansion bus. This bridge logic is sometimes referred to as a “South bridge” reflecting its location vis-a-vis the North bridge in a typical computer system drawing. An example of such bridge logic is described in U.S. Pat. No. 5,634,073, assigned to Compaq Computer Corporation. In
FIG. 1
, the South bridge couples the PCI bus to an ISA bus. Various ISA-compatible devices are shown coupled to the ISA bus.
The North bridge typically incorporates a memory controller which receives memory access requests and generates standard control signals on the memory bus necessary to access the memory. The memory subsystem typical of most personal computers generally permits only one memory transaction to occur at a time. The North bridge, however, represents a central point through which all requests for memory (either to write data to or read data from memory) must pass. Because many of the devices in a typical computer system, such as those shown in
FIG. 1
, may need to access memory, the memory controller in the North bridge performs an arbitration function to decide which device in the computer system will be permitted access to memory.
The arbiter in an exemplary memory controller typically implements a predetermined algorithm for deciding which one of a number of pending memory requests to execute (“service”) next. The arbitration decision is repeated at regular intervals, often every 10 nanoseconds (10×10
−9
seconds) or so. A number of steps occur in each arbitration interval. For example, the memory controller may compare the memory address of the request that won arbitration with the previously accessed memory addresses to determine if a match exists. If a match does exist, one or more clock cycles can be saved in set up time for the memory address. As the number of devices that may need access to memory increases in a computer system, the ability of the memory controller to arbitrate and then respond to the winning request in a timely fashion becomes increasingly more difficult.
Memory arbitration typically occurs “synchronously.” That is, the arbiter receives the pending memory requests and, at one time decides to which request to award arbitration. This decision is synchronized to an “edge” of a clock signal. A clock signal is a voltage signal whose magnitude toggles (or oscillates) between two voltage levels in a rhythmic, repeating pattern. The winner of arbitration is decided on a rising or falling edge of the clock signal. Memory controllers usually respond to the winning memory request within the next clock cycle. If the clock is a 100 megahertz signal (i.e., the clock signal includes 100 million cycles per second, the memory controller thus would have to respond to the winning request within one cycle, or 10 nanoseconds. Although the amount of time to arbitrate and then respond to a winning memory request may have been sufficient for early computer systems, it is increasingly more difficult to accomplish these tasks in current computer systems which include more and more components requiring access to memory.
For the foregoing reasons, a computer system that includes a memory controller that alleviates the burden described above of previous memory controllers is needed. Such a memory controller would preferably include an arbitration unit that permits sufficient arbitration of the pending memory requests. Unfortunately, to date, no such device is known that provides these features.
SUMMARY OF THE INVENTION
Accordingly, there is provided herein a computer system that includes a CPU, a memory device or array and a memory controller for controlling access to the memory. The computer system preferably includes other devices that may access memory through the memory controller. The memory controller generally includes a memory arbiter comprising arbitration logic for deciding which memory request among one or more pending requests should win arbitration and thereby be given access to memory. When a request wins arbitration, the arbitration logic asserts a “won” signal corresponding to that memory request. The won signal is provided to other logic in the memory controller which performs the memory request.
In accordance with the preferred embodiment, the memory controller also includes synchronizing logic to synchronize memory requests, corresponding to a first group of requests, that win arbitration to an arbitration enable signal generated by the memory arbiter and an edge of a clock signal. The synchronizing logic includes a logic gate, preferably an AND gate, and a latch for synchronizing the won signals to the clock edge. The won signal is asserted by arbitration logic which selects the winning memory request to be logically ANDed with the arbitration enable signal. Then, the synchronized won signal is clocked through the latch to synchronize the won signal and provided as an output signal from the synchronizing logic. Thus, the synchronized won signals are asserted preferably on the first clock edge following the initial assertion of the arbitration enable signal. The synchronized won signals thus are asserted one clock cycle after the enable signal becomes active.
The memory controller also asynchronously arbitrates a second group of memory requests. The arbitration logic also generates won signals associated with this second group of memory requests. The won signals pertaining to the second group to be asynchronously arbitrated are provided to an OR gate to. The won signals preferably are also processed by the synchronization logic described above. The synchronized second group won signals are also provided to the OR gate which asserts its output signal when either the unsynchronized or synchronized won signals become active. By OR'ing together the synchronized and unsynchronized second group won signals, the won signals for the second group of requests can be assert
Chin Kenneth T.
Collins Michael J.
Jones Phillip M.
Lester Robert A.
Piccirillo Gary J.
Compaq Computer Corporation
Conley & Rose & Tayon P.C.
Harris Jonathan M.
Heim Michael F.
Nguyen Than
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