Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-12-29
1998-10-13
Gossage, Glenn
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711137, 711119, G06F 1300
Patent
active
058227571
ABSTRACT:
A computer system including a multi buffer data cache and method of caching data based on predicted temporal and spatial localities. A processor operates on operands under instruction control, the operands being stored in a main memory. The processor is coupled to the main memory via a data cache for prefetch and storage of operands referenced by the instructions. The data cache comprises an S-buffer for storing operands with strong temporal locality, and a P-buffer for storing operands with strong spatial locality. A control unit connected to the processor, the buffers and the main memory, determines what type of locality is involved in the operand referenced, based on whether the instruction accesses the main memory in a direct or indirect addressing mode as determined by a decoder unit of the processor, and governs operation of the buffer associated with the type of locality determined. Data references may be classified into a plurality of groups, which may include data references to stack data or global variable data, on the basis of predicted statistical associations of localities of the data references. The processor may include a stack pointer register and the computer system may identify requests using the indirect addressing mode based on the stack pointer register.
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Gossage Glenn
Philips Electronics North America Corporation
Wieghaus Brian J.
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