Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1999-12-17
2003-07-15
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S144000, C711S158000, C710S035000, C710S244000
Reexamination Certificate
active
06594732
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a computer system. More particularly, the present invention relates to a computer system having a memory system having a write back type cache memory.
2. Description of the Related Art
In a memory system for a high speed operation, SRAM (Synchronous DRAM) is typically used for a cache memory, DRAM is used for a main memory, and a write back system is employed.
In the write back system, there is a case that a data written in the cache memory is not immediately written back to the main memory so that a device (hereafter, referred to as a processor) can carry out a memory access at high speed. Accordingly, the cache memory and the main memory sometimes have data different from each other. This inconsistent state is referred to as a “dirty” state. On the contrary, the consistent state is referred to as a “clean” state.
FIGS. 1A
to
1
H show the write back operation in a typical computer system with a main controller. Referring to
FIGS. 1A
to
1
H, a main controller typically expects a page hit to the main memory, and waits for a next memory access without carrying out the access while keeping the same row address active. This is carried out not only in the case of the write back operation, but also after the end of the main memory access. This is because the access can be carried out from a column cycle without need of a pre-charging operation, if an access to the same row address, i.e., the page hit occurs. Upon occurrence of an access of page miss, the row address is switched in accordance with the standard of DRAM. In this case, a RAS signal (row address strobe signal) is again outputted, i.e., the pre-charging operation is carried out again, and then the access is carried out.
It is necessary to carry out the write back operation to the main memory in case of a cache memory miss hit. In this case, a data to be abandoned in order to store a new data in the cache memory is written in the main memory. The write back operation to the main memory is carried out under a control of a memory controller, and carried out to only a cache memory area in the dirty state. This write back operation must be always carried out in order to write a correct data to the main memory. For this reason, the write back operation can not be interrupted even if a new memory access is requested from a CPU during the write back operation. Thus, the write back operation occupies a memory bus for a period of the write back operation. Therefore, it is not effective to carry out the write back operation for each cache memory miss hit, even if it is necessary. The reason is that a necessary process can not be forwarded while the write back operation is carried out.
The proposals to improve an efficiency of a computer system using the write back type cache memory are disclosed in Japanese Laid Open Patent Application (JP-A-Heisi 4-69750), Japanese Laid Open Patent Application (JP-A-Heisi 6-309231) and the like.
In the Japanese Laid Open Patent Application (JP-A-Heisei 5-20195), a page mode is used to carry out the write back operation. In the Japanese Laid Open Patent Application (JP-A-Heisei 4-69750), the write back operation and a reading out operation are continuously carried out if the write back operation and the reading out operation have the same row address. However, these two conventional examples are intended to improve the efficiency of the write back operation itself. They can not solve the problem that the necessary process can not be carried out while the write back operation is carried out.
In the Japanese Laid Open Patent Application (JP-A-Heisei 6-309231), an empty time of a bus is used to carry out the write back operation. If the write back operation is carried out by use of the empty time of the bus, the efficiency of the computer system can be improved as a whole because other processes are not disturbed. However, in the Japanese Laid Open Patent Application (JP-A-Heisei 6-309231), the write back operation using the empty time of the bus is autonomously started in a predetermined period. That is, it is checked whether or not the bus is empty, at every predetermined period. If the bus is empty, the write back operation is carried out. On the contrary, if the bus is not empty, the write back operation is not carried out, and the operational flow waits for a next period. For this reason, it is necessary to periodically check whether or not the bus is empty. Moreover, the write back operation itself is carried out by use of a procedure similar to the conventional write back operation. Thus, it does not improve the efficiency of the write back operation itself. Furthermore, the write back operation is not carried out if the bus is not empty. Hence, it is impossible to cope with the cache memory areas at the dirty state surely and quickly.
In conjunction with the above description, a DRAM control system is described in Japanese Laid Open Patent Application (JP-A-Heisei 7-271666). In the reference, there are two registers: one storing an address data in a range of the line size of a cache memory and the other storing an address data out of the range of the line size of the cache memory. When a snoop process is generated, an address information on a bus is held by the two registers and an active command is inputted. When the write back cycle is generated, only the address data in a range of the line size of the cache memory is held by the register and a write command is inputted. Thus, the active command to a synchronous DRAM can be inputted during the snoop process before the access to a main memory unit by a bus master is started. Therefore, when the write back cycle is carried out, the active command can be omitted, resulting in improvement of efficiency.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a computer system with a memory system having a write back type cache memory.
Another object of the present invention is to provide a computer system with a memory system in which a cache line in a write back type cache memory can be kept as clean as possible.
In order to achieve an aspect of the present invention, a computer system includes a host bus, a CPU connected to the host bus, a main memory connected to the host bus, a cache memory and a memory controller. The cache memory is connected to at least one of the host bus and the CPU, stores cache data. A tag address and a flag are provided for each of the cache data and the flag indicates one of a clean state in which the corresponding cache data is written back into the main memory and a dirty state in which the corresponding cache data is not yet written back into the main memory. The memory controller is connected to the host bus, the cache memory and the main memory. The memory controller writes back dirty write back cache data into the main memory in a continuous write back mode, when the host bus is not used, wherein the dirty write back cache data is a part of the cache data stored in the cache memory, and each of the dirty write back cache data is not written back and includes a predetermined portion in the tag address.
The CPU accesses the cache memory or the main memory in a memory access using the host bus, and the predetermined portion is a row address of a physical address in the latest memory access. It is preferable that the memory controller holds the row address in the continuous write back mode.
The memory controller may cancel the continuous write back mode when the CPU accesses the cache memory or the main memory in a memory access using the host bus. In this case, the memory controller includes an address decoder connected to the host bus. The address decoder decodes a logical address on the host bus into a physical address and detects the memory access by the CPU. The memory controller cancels the continuous write back mode when the memory access is detected by the address decoder. In this case, the predetermined portion may be a row address of the physical address in the latest memory access. Al
Kim Matthew
Tran Denise
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