Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Patent
1998-03-13
2000-05-30
Sheikh, Ayaz R.
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
713320, G06F 1338
Patent
active
06070215&
ABSTRACT:
A computer system includes a South bridge logic device that monitors the FLUSHREQ signal and masks that signal when the CPU transitions the computer to a low power mode of operation. Once masked, the FLUSHREQ cannot be asserted to the North bridge and the conflict between attempts by the CPU and an ISA device to run cycles on the PCI bus is avoided. The South bridge also masks all requests to run cycles on the PCI bus that are not originated by the CPU. The South bridge includes a programmable control register and a PCI arbiter. When a control bit is set in the register, the PCI arbiter waits for FLUSHREQ to be deasserted and then masks FLUSHREQ. The PCI arbiter preferably also disables PCI arbitration by masking all non-CPU. Only the CPU can run PCI cycles when the non-CPU requests are masked. The programmable control register also includes a masking status bit that is set when both the FLUSHREQ and non-CPU request signals are masked by a request mask state machine. The computer system may also include a laptop computer docked to an expansion base with a South bridge included in the computer and the expansion base.
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VLSI Digital Signal Processors by Vijay K. Madisetti (Georgia Institute of Technology) Chapter 3, pp. 61-63; Butterworth-Heinemann.
Deschepper Todd J.
Elliott Robert C.
Compaq Computer Corporation
Harris Jonathan M.
Heim Michael F.
Pancholi Jigar
Sheikh Ayaz R.
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