Computer system with dram bus

Details Computer system with dram bus Computer system with dram bus

2000-07-11

2002-09-03

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S101000, C711S104000, C711S105000

Reexamination Certificate

active

06446174

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of computer systems; more particularly, to computer memory systems and memory architectures that provide expanded memory capacity at high data rates.
BACKGROUND OF THE INVENTION
The faster speeds of modern data processing systems has led to the development of new memory systems that can provide data at faster rates. To achieve faster data rates, many of today's computer systems include a host processor connected to a memory controller that controls access to a memory subsystem, which may comprise dynamic random-access memory (DRAM) devices. An example of such system is found in U.S. Pat. No. 5,828,881, which teaches a memory system that employs high-speed DRAM or Rambus™ memory (RDRAM) technology. Rambus™ is a trademark of Rambus, Inc., of Mountain View, Calif. Another technology, known as Direct RDRAM™ (Rambus dynamic RAM), employs interleaved banks of dynamic random-access memory cells that can be rapidly accessed. For example, U.S. Pat. No. 5,889,726 discloses the use of a memory controller for accomplishing fast memory read and write operations to a memory having a synchronous clocked interface, which may include a Rambus interface.
It is known that a number of such memory devices may be connected to a memory channel, e.g., a Direct Rambus™ channel or Direct RDRAM™ channel, according to a specified protocol. By way of background, U.S. Pat. No. 6,003,121 provide examples in which memory repeater hubs are utilized in various memory system configurations with Direct RDRAM™ channels to achieve expanded memory capacity. U.S. Pat. No. 5,828,382 also describes a graphics display system in which data is transferred through a memory controller to Rambus RDRAMs.
FIG. 1
illustrates a typical prior art memory system
10
, which includes a memory controller hub (MCH)
11
that communicates with a memory repeater hub (MRH)
12
via a Rambus channel
14
. Rambus channel
14
allows communication back and forth between MCH
11
and MRH
12
according to a specified protocol. At present, up to two memory repeater hubs may be connected to a single Rambus channel
14
. Essentially, MRH
12
achieves a 2:1 multiplexing of the channel lines, such that MRH
12
provides two RDRAM Rambus channels
15
a
&
15
b
that communicate with the actual Rambus RDRAM devices.
As is well understood, the RDRAM Rambus channel operates in accordance with a separate protocol that differs from the protocol specified for the Rambus channel output from MCH
11
. In other words, according to Rambus memory technology there is one protocol for communicating with RDRAM devices, and another, different protocol used to communicate with the memory repeater hubs. The design of MCH
11
is such that it permits communications directly to the RDRAMs and also to the MRHs.
Despite the widespread use of RDRAM technology, the number of memory repeater hubs that can be connected to a single Rambus channel remains limited. Present memory system implementations are restricted to a maximum of four RDRAM channels. Thus, there exists an unfulfilled need for new devices or system configurations to expand the number of RDRAM channels which can be supported.


REFERENCES:
patent: 5815168 (1998-09-01), May
patent: 5828881 (1998-10-01), Wang
patent: 5889726 (1999-03-01), Jeddeloh
patent: 5969728 (1999-10-01), Dye et al.
patent: 6003121 (1999-12-01), Wirt

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