Computer system with bridges having posted memory write buffers

Details Computer system with bridges having posted memory write buffers Computer system with bridges having posted memory write buffers

1999-03-02

2000-07-04

Myers, Paul R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

370402, G06F 1300

Patent

active

060852747

ABSTRACT:
A computer system using posted memory write buffers in a bridge can implement the system management mode without faulty operation. The system management interrupt acknowledge signal is posted in bridge buffers so that any previously posted memory write commands currently held in a posted memory write buffer in the bridge execute prior to the appearance of the posted system management interrupt acknowledge signal. In this way, devices on a downstream bus will not be confused by the occurrence of posted memory write transactions into mistaking such transactions for system management mode operations. In this way, both bridges having posted write buffers and the system management mode may be utilized in efficient joint operation.

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patent: 6021451 (2000-02-01), Bell et al.

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