Computer system with bridge logic that reduces interference to C

Details Computer system with bridge logic that reduces interference to C Computer system with bridge logic that reduces interference to C

1998-03-13

1999-11-23

Thai, Xuan M.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

710112, 710128, 710129, G06F 1338

Patent

active

059918330

ABSTRACT:
A computer system includes a CPU and a memory device coupled through a North bridge logic device. The computer also includes a South bridge logic device coupled to the North bridge by a primary bus. The South bridge waits as long as possible before asserting a flush request (FLUSHREQ) control signal to the North bridge. The South bridge asserts the FLUSHREQ signal to the North bridge after a peripheral device coupled to the South bridge requests access to the primary bus to run a cycle. The South bridge first flushes a write queue before asserting the FLUSHREQ signal to the North bridge. In response to the FLUSHREQ control signal, the North bridge flushes one or more of its own internal write queues in preparation for the upcoming peripheral device cycle. By flushing its own internal write queue before asserting FLUSHREQ to the North bridge, the South bridge reduces the amount of time that the CPU will be prevented from accessing the primary expansion bus while the peripheral device attempts to run a cycle on the primary bus. An alternative embodiment of the invention includes a pair of South bridges, one South bridge in a laptop computer and the other South bridge in an expansion base to which the laptop computer mates.

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VLSI Digital Signal Processors by Vijay K. Madisetti (Georgia Institute of Technology) Chapter 3, pp. 61-63; Butterworth-Heinemann, dated 1995.

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