Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
2011-06-07
2011-06-07
Cleary, Thomas J (Department: 2111)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
C713S501000, C713S502000
Reexamination Certificate
active
07958383
ABSTRACT:
A computer system has an adjustable data transmission rate between a CPU and a core logic chip thereof. In the computer system, the CPU has a power state adjustable in response to a power management control signal issued by the core logic chip. For adjusting data transmission rate between the CPU and the core logic chip, a change of an asserted time of the power management control signal from a first time period to a second time period is first determined to obtain an index value. The data transmission rate is increased or decreased according to the index value.
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Chang Chi
Chung Chien-Ping
Huang Cheng-Wei
Cleary Thomas J
Kirton & McConkie
VIA Technologies Inc.
Witt Evan R.
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