Computer system with a data cache for providing real-time multim

Details Computer system with a data cache for providing real-time multim Computer system with a data cache for providing real-time multim

1996-05-17

1999-04-27

Lee, Thomas C.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

39580035, 39580034, 395281, 711118, 711127, 711146, G06F 1312

Patent

active

058988920

ABSTRACT:
A computer system and method optimized for real-time multimedia applications are presented. The computer system, including a dedicated multimedia engine coupled directly to a real-time data cache, provides increased performance over current computer architectures. The multimedia engine includes at least one DSP engines which couple through at least one I/O channels to I/O ports. Obtaining multimedia commands and data from main memory and/or the real-time data cache, the multimedia engine performs a number of multimedia operations including audio and video functions. A CPU, coupled through a chip set logic or bridge logic to the main memory, generates multimedia commands and data. The CPU groups multimedia commands and data into separate command and data elements, and writes the command and data elements to a multimedia address space in main memory. The CPU also writes element structure information to the multimedia address space. The element structure information includes location information used to retrieve multimedia commands and data from main memory. The real-time data cache allows multimedia data from an external source to be stored in a location other than main memory, and allows this multimedia data to be shared by the CPU and the multimedia engine. The real-time data cache may also store multimedia commands and data for use by the multimedia engine.

REFERENCES:
patent: 4245344 (1981-01-01), Richter
patent: 4991169 (1991-02-01), Davis et al.
patent: 5208745 (1993-05-01), Quentin et al.
patent: 5245322 (1993-09-01), Dinwiddie, Jr. et al.
patent: 5261072 (1993-11-01), Siegel
patent: 5287484 (1994-02-01), Nishi et al.
patent: 5325423 (1994-06-01), Lewis
patent: 5373493 (1994-12-01), Iizuka
patent: 5375220 (1994-12-01), Ishikawa
patent: 5404522 (1995-04-01), Carmon et al.
patent: 5440336 (1995-08-01), Buhro et al.
patent: 5440740 (1995-08-01), Chen et al.
patent: 5440755 (1995-08-01), Harwer et al.
patent: 5448735 (1995-09-01), Anderson et al.
patent: 5450551 (1995-09-01), Amini et al.
patent: 5461679 (1995-10-01), Normile et al.
patent: 5487167 (1996-01-01), Dinallo et al.
patent: 5497373 (1996-03-01), Hulen et al.
patent: 5508940 (1996-04-01), Rossmere et al.
patent: 5519345 (1996-05-01), Farrell et al.
patent: 5519839 (1996-05-01), Culley et al.
patent: 5530835 (1996-06-01), Vashi et al.
patent: 5530902 (1996-06-01), McRoberts et al.
patent: 5535339 (1996-07-01), Kim
patent: 5551009 (1996-08-01), Amini et al.
patent: 5557757 (1996-09-01), Gephardt et al.
patent: 5564001 (1996-10-01), Lewis
patent: 5574662 (1996-11-01), Windrem et al.
patent: 5623633 (1997-04-01), Zeller et al.
patent: 5692211 (1997-11-01), Gulick et al.
patent: 5732224 (1998-03-01), Gulick et al.
patent: 5748983 (1998-05-01), Gulick et al.
Horning et al., "Hewlett-Packard's New Multimedia Enabled PA-RISC Workstations," pp. 362-368, IEEE Computer Society Press, Feb. 1994.
Kettler, Kevin A. and Jay K. Strosnider, "Scheduling Analysis of the MicroChannel Architecture for Multimedia Applications," Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, May 1994, pp. 403-414.
Weiss, Ray, Senior Editor, "DSP tools: navigating the hardware/software interface," Computer Design, Oct. 1994, pp. 69-88.
Lee, et al., "Real-time MPEG Video Codec on a Single-chip Multiprocessor," SPIE vol. 2187, Apr. 1994, pp. 32-42.
Horning, et al., "Hewlett-Packard's New Multimedia Enabled PA-RISC Workstations," Feb. 28, 1994, pp. 362-368.
Bursky, D., "Advanced CPUS, Multimedia ICS Deliver Top Throughputs," vol. 44, No. 4, Feb. 19, 1996, pp. 55, 56, 58, 62, 64-66, 68, 70 & 74.
Norrod, F. et al., "A Multimedia-Enhanced X86 Processor," 1996 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, ISSCC, First Edition (Cat. No. 96CH35889), 1996 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, ISSCC, San Francisco, CA USA, 8-10 FE, ISBN 0-7803-3136-2, pp. 220-221 & 449.
Halfhill, T.R., "AMD K6 Takes on Intel P6," Byte, vol. 21, No. 1, Jan. 1, 1996, pp. 67, 68, 70 & 72.
International Search Report for PCT/US 97/01068 mailed Jun. 17, 1997.
PCI Local Bus--PCI Multimedia Design Guide--Revision 1.0--Mar. 29, 1994, 41 pages.

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