Computer system with a cache coherent non-uniform memory access

Details Computer system with a cache coherent non-uniform memory access Computer system with a cache coherent non-uniform memory access

1996-06-11

1998-07-28

Robertson, David L.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711148, G06F 1300

Patent

active

057874689

ABSTRACT:
A fast tag cache is an array to cache a limited set of identifiers specifying the residency and access rights to memory blocks and cache blocks contained in a node within a distributed memory system built using a cache coherent non-uniform memory access architecture. The purpose of the fast tag array is to ensure peak processor-memory bus throughput each node and minimize the amount of memory required to hold cache state information.

REFERENCES:
patent: 4483003 (1984-11-01), Beal
patent: 5265235 (1993-11-01), Sindhu et al.

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