Computer system with a bus having a segmented structure

Details Computer system with a bus having a segmented structure Computer system with a bus having a segmented structure

1998-07-09

2001-11-06

Thai, Xuan M. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S241000

Reexamination Certificate

active

06314484

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a computer system, and in particular to a computer system with a segmented bus.
BACKGROUND OF THE INVENTION
The architecture of a computer system typically comprises a bus structure consisting of a plurality of transmission lines to which various units are connected in parallel. In a computer system which includes a large number of units, as in a multi-processor system for example, the physical length of the bus becomes rather large. A disadvantage of this structure consists in the fact that the length of the bus increases the signal propagation time; this reduces the operating frequency of the bus, since the duration of an operating cycle is inevitably greater than this propagation time. Furthermore, since the same data item is distributed simultaneously to all the units connected to the bus, the structure is affected by the electrical load (input impedance) introduced by these units; this makes it necessary to use driver circuits with relatively high power and consequently high consumption, and creates a non-uniform distribution of the electrical load which may give rise to phenomena of reflection. The bus therefore has a low transfer rate, which has a marked effect on the performance of the whole computer system.
A further disadvantage is manifested in the case in which the bus (known as the remote bus) is used to connect nodes which comprise different units interconnected by means of a further bus (called the local bus).
The nodes are connected to the system or remote bus by a device which acts as a bridge between the local bus and the remote bus.
Each node corresponds to a single load (that of the bridge) connected to the remote bus.
In this way it is possible to reduce the number of loads connected to the bus and to improve its performance.
However, the remote bus generally has a greater length than the local buses, and therefore its operating speed is lower; this means that whenever a node accesses the remote bus it is necessary to introduce a latency period of a few operating cycles of the local bus.
SUMMARY OF THE INVENTION
The object of the present invention is to overcome the aforesaid disadvantages.
Essentially, the system bus, or remote bus, is divided into a plurality of segments of reduced length, linked in series and interconnected by pairs of buffer registers which transfer data from one bus segment to those immediately adjacent, in one or other of the two possible directions (for this purpose, the inter-connection between two segments is provided by pairs of buffers, one for the transfer of data in one direction, and the other for the transfer in the opposite direction).
The buffers are controlled by an arbitration unit, timed by a periodic clock signal, to store the data present in one bus segment in one period of the clock signal, with the leading edge of the clock signal which terminates the period and starts the next, and to transfer the data thus stored to the adjacent bus segment with the same leading edge of the clock signal.
It is thus evident that at least N−1 periods of the clock signal are required to transfer a data item along N concatenated bus segments.
However, it is evident that up to N different data items may pass simultaneously through the different segments of the bus in both directions, with a substantial increase in the transfer rate.
The arbitration unit, using suitable arbitration algorithms, determines the order in which the different data items are transferred from one segment to another in such a way as to provide the best possible transfer rate in different circumstances.


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