Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
1998-05-08
2001-11-13
Sheikh, Ayaz (Department: 2155)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S320000, C713S324000, C713S300000, C713S501000, C713S502000, C713S600000
Reexamination Certificate
active
06317841
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a computer system such as a personal computer and, more particularly, to a computer system using a stop clock function in the system to realize a power saving mode.
2. Description of the Related Art
In recent years, various notebook or laptop type portable personal computers which allow easy transport and an operation with batteries have been developed. In a computer of this type, various power saving means have been examined to make the battery drive time as long as possible.
For example, to decrease the power consumption of a CPU, the CPU operation speed is decreased to minimize the current consumption of the CPU.
A technology for controlling the CPU operation speed is disclosed in U.S. Pat. No. 5,125,088, for example. The speed control of the microprocessor will now be described with reference to
FIGS. 1 and 2
.
The speed control of the microprocessor can be initiated by either the floppy drive motor spin-up or enable
2
or the speed control software
4
. The computer operator interacts with the computer through a utility program to set the speed of the microprocessor. This action by an operator is represented in
FIG. 1
by block
4
.
As illustrated in
FIG. 1
, the floppy drive enable
2
is logically ORed with the software controlled speed control
4
and logically ANDed with the speed control bypass switch
2
. In the event the bypass switch
2
is closed, the speed control mechanism is inoperative. The speed control command is then logically ANDed with the speed control timer
8
, therefore, the CPU HOLD output to the CPU remains active for as long as the timer remains active.
The speed control command is logically ORed with the arbitrated output of the arbitration logic of the DMA request
10
and the REFRESH request
12
.
The DMA request/REFRESH request is arbitrated by arbitrator logic
14
to prevent both a DMA and REFRESH request from occurring simultaneously.
The HOLD request
16
to the CPU can be generated by either the REFRESH request, DMA request or the speed control logic. As will be described infra these holds cannot occur simultaneously because of the logic which controls each function.
The speed control is initiated by the following four CPU instructions:
1) MOV AL, 92H
2) OUT 4BH, AL
3) MOV AL, XX
4) OUT 4AH, AL
The one-shot time delay set in the speed control timer is set by instruction 3. Address 4BH in instruction 2 is the control word register.
The speed adjustment software controls the setting of the one-shot timer. The operator of the machine selects a time delay setting by selecting one of the arbitrary designations set forth below:
COMMON
FAST
HIGH
or by selecting a speed setting from 1 to 50 where the setting “1” corresponds to the slowest machine speed which can be simulated by this microprocessor and “50” corresponds to the highest speed which can be simulated by this microprocessor.
It should be noted that the designation “COMMON” will simulate a microprocessor speed equivalent to an 80286 microprocessor operating at a 6 MHz clock rate; the designation “FAST” will simulate a microprocessor speed equivalent to an 80286 microprocessor operating at an 8 MHz clock rate; the designation “HIGH” will simulate the microprocessor speed of an 80386 microprocessor operating at the 16 MHz clock rate; full speed of an 80386 microprocessor.
The arbitrary speed designation of “3” on a scale of 1 to 50 corresponds to the simulated speed of an 8088 microprocessor and the arbitrary speed designation of “50” on a scale of 1 to 50 corresponds to the designation “HIGH” described above.
The one-shot timer is set by setting register AL to the required hexadecimal value which corresponds to an operator's selection of either a value of “COMMON”, “FAST” or “HIGH” or by an operator's selection of a decimal number in the range of 1-50.
The one-shot timer is set by setting register AL to a hexadecimal value corresponding to the “FAST” mode whenever the floppy drive motor is enabled. Enabling the floppy drive motor reduces the apparent microprocessor speed since most floppy drive operations indicate either a transfer of data from a copy-protected diskette or other diskette operation which cannot be performed at the full 80386 processor speed.
In
FIG. 2
, a 4 MHz clock range is illustrated as “DCLK”. Each square wave represents 250 microseconds.
3-1: The REFRESH request occurs once every 15 microseconds. This request is arbitrated with the Direct Memory Access (DMA) request to prevent simultaneous requests. The REFRESH request is then logically ORed with the other request sources to generate the CPU “HOLD” request.
3-2: Sometime after the HOLD request is generated and after the current CPU by cycles have been completed, the CPU will stop executing the program and grant the HOLD acknowledge (ACK).
3-3: The HOLD ACK is logically gated with the arbitrated REFRESH request to form the REFRESH acknowledge (ACK) signal to the REFRESH controller.
3-4: The REFRESH ACK signal triggers the digital one-shot which in turn sets the STOP request signal active. Since the REFRESH request is still present (high), there is no change in the CPU state.
3-5: The REFRESH controller executes the rEFRESH cycle on the system bus and then releases the REFRESH request.
3-6: Release of the REFRESH request also releases the REFRESH ACK signal and ends the REFRESH portion of the cycle. (If the STOP request is not present, then the HOLD request is released and the CPU begins executing again).
3-7: During the duration of the one-shot timeout, the STOP request remains active and the CPU cannot run bus cycle (i.e., execute code). This timeout value is variable from 0 duration (e.g., CPU begins executing immediately after REFRESH equivalent to full speed microprocessor cycle) through 15 microseconds where the CPU never gets a change to execute another REFRESH and STOP cycle will begin as soon as the last cycle is completed (e.g., the microprocessor fully stopped). Choosing values between 0 and 15 microseconds the STOP request will be dropped when the one-shot times out.
3-8: Release of the STOP request causes the HOLD request to be dropped.
3-9: The CPU responds by dropping the HOLD ACK. The CPU begins executing the program again (i.e., executing code or programs steps).
3-10: 15 microseconds from the original REFRESH request, the next REFRESH request will arrive and the cycle will repeat itself.
The use of the microprocessor HOLD or STOP permits time dependent operations to be handled by the 32-bit microprocessor which is operating at a constant clock rate, in this case 16 MHz, without slowing the microprocessor down to a slower clock rate. The use of a slower clock rate has been previously suggested however this method of operating is not acceptable in an 80386 environment because it has the effect of slowing down all operations, not just those which are time dependent. Thus, in the typical application, the microprocessor is placed on HOLD only for so long as necessary to simulate the microprocessor speed which is necessary to perform time dependent functions.
Alternatively, the operation of the microprocessor can be placed in a deliberately slow mode by causing the one-shot timer to be re-initiated as soon as it is released. This is accomplished in software and once this software is executed, the operator selects a speed ranging from 1 to 50, or in the alternative specific speed designations which have been arbitrarily set. In this case the following speeds have been arbitrarily set which correspond to the speeds indicated below:
COMMON-Approximately equivalent to a speed setting of an 80286 microprocessor operating at clock rate of 6 MHz.
FAST-Approximately equivalent to a speed setting of an 80286 microprocessor operating at a clock rate of 8 MHz.
HIGH-Approximately equivalent to a speed setting of an 80386 microprocessor operating at a clock rate of 16 MHz.
The CPU HOLD request can be generated by either the arbitrated REFRESH request, the arbitrated DMA system request or the system speed control.
The s
Iguchi Takeyuki
Nagae Akihito
Senuma Koichi
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Jean Frantz B.
Kabushiki Kaisha Toshiba
Sheikh Ayaz
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