Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2005-11-30
2009-02-03
Phan, Raymond N (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S016000, C710S033000, C710S038000, C710S107000, C710S316000
Reexamination Certificate
active
07487281
ABSTRACT:
In a computer system that includes a memory, a peripheral device to which an address overlapping with a part of an address space assigned to the memory is assigned, a CPU for sending a signal responding an address of an access destination to a bus when the CPU accesses either the memory or the peripheral device, and a bus for connecting the CPU and the peripheral device, a switch for switching a connection and a disconnection between the CPU and the memory via the bus, and an interface portion for receiving a signal sent to the bus from the CPU and specifying an address indicated by the signal and a decoding portion for turning OFF the switch when the address specified by the interface portion is the address assigned to its own device is provided to the peripheral device.
REFERENCES:
patent: 6954821 (2005-10-01), Fitzsimmons et al.
patent: 7376777 (2008-05-01), Coffee et al.
patent: 50-74349 (1975-06-01), None
patent: 06-332796 (1994-12-01), None
patent: 2002-132580 (2002-05-01), None
Okamoto Kazuki
Suzuki Tomohiro
Phan Raymond N
Pillsbury Winthrop Shaw & Pittman LLP
Yamaha Corporation
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