Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Patent
1997-12-02
2000-05-02
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
711137, 711151, G06F 1318
Patent
active
060584610
ABSTRACT:
A computer system includes one or more microprocessors. The microprocessors assign a priority level to each memory operation as the memory operations are initiated. In one embodiment, the priority levels employed by the microprocessors include a fetch priority level and a prefetch priority level. The fetch priority level is higher priority than the prefetch priority level, and is assigned to memory operations which are the direct result of executing an instruction. The prefetch priority level is assigned to memory operations which are generated according to a prefetch algorithm implemented by the microprocessor. As memory operations are routed through the computer system to main memory and corresponding data transmitted, the elements involved in performing the memory operations are configured to interrupt the transfer of data for the lower priority memory operation in order to perform the data transfer for the higher priority memory operation. While one embodiment of the computer system employs at least a fetch priority and a prefetch priority, the concept of applying priority levels to various memory operations and interrupting data transfers of lower priority memory operations to higher priority memory operations may be extended to other types of memory operations, even if prefetching is not employed within a computer system. For example, speculative memory operations may be prioritized lower than non-speculative memory operations throughout the computer system.
REFERENCES:
patent: 4729093 (1988-03-01), Mothersole et al.
patent: 4755933 (1988-07-01), Teshima et al.
patent: 5367657 (1994-11-01), Khare et al.
patent: 5619663 (1997-04-01), Mizrahi-Shalom et al.
patent: 5673415 (1997-09-01), Nguyen et al.
patent: 5721865 (1998-02-01), Shintani et al.
Tullsen et al., Exploiting Choice:Instruction Fetch and Issue on an Implementable Simultaneous Mutithreading Processor Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, May 1996, pp. 191-202 [Online] http://www.cs.washington.edu/research/smt.
Lewchuk W. Kurt
McMinn Brian D.
Pickett James K.
Advanced Micro Devices , Inc.
Chan Eddie P.
Encarnacion Yamir
Merkel Lawrence J.
LandOfFree
Computer system including priorities for memory operations and a does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Computer system including priorities for memory operations and a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computer system including priorities for memory operations and a will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1602393