Computer system including an apparatus for reducing power consum

Details Computer system including an apparatus for reducing power consum Computer system including an apparatus for reducing power consum

1995-04-03

1998-04-07

Gossage, Glenn

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

39575006, 365227, G06F 1300, G06F 126, G11C 11413, G11C 700

Patent

active

057377464

ABSTRACT:
A computer system includes an apparatus for conserving power in a tag static random access memory (SRAM). The computer system includes circuitry for placing the tags of the tag SRAM in a reduced power consumption state. The computer system also includes circuitry to power up the tag SRAM out of the reduced power consumption state while maintaining the integrity of the data stored in the tags. The computer system includes a bus, a processor, a cache memory and a memory controller. The memory controller is comprised of a tag static random access memory (SRAM) which includes sense amplifier circuitry and control logic for activating the tag SRAM in response to an address strobe signal (ADS#) from the processor initiating access to the tag SRAM. The memory controller further includes control logic for keeping the tag SRAM activated during an access cycle and for deactivating the tag SRAM, including the sense amplifier circuitry, upon completion of an access cycle to the tag SRAM, thereby placing the tag SRAM in a reduced power consumption state.

REFERENCES:
patent: 4932001 (1990-06-01), Chow et al.
patent: 5018061 (1991-05-01), Kishigami et al.
patent: 5325335 (1994-06-01), Ang et al.

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